Intel Arria 10 User Manual

For the Native PHY IP, you can control the embedded streamer block through the
reconfiguration interface. Control and status signals of the streamer block are memory
mapped in the PHY’s soft control and status registers. These embedded
reconfiguration control and status registers are replicated for each channel. You
cannot merge reconfiguration interfaces across multiple IP cores when the embedded
reconfiguration streamer is enabled because the embedded reconfiguration streamer
makes use of soft logic for control and status registers.
You can optionally allow the Native PHY IP core to include PMA Analog settings in the
configuration files by enabling the feature Include PMA Analog settings in
configuration files in the Dynamic Reconfirmation tab of the Transceiver Native
PHY IP Parameter Editor. This feature is disabled by default. Enabling this feature adds
the PMA analog settings specified in the Analog PMA settings (Optional) tab of the
Native PHY IP Parameter Editor to the configuration files. Even with this option
enabled in the Native PHY IP Parameter Editor, you must still specify QSF assignments
for your analog settings when compiling your static design. The analog settings
selected in the Native PHY IP Parameter Editor are used only to include these settings
and their dependent settings in the selected configuration files. For details about QSF
assignments for the analog settings, refer to the Analog Parameter Settings chapter.
For example, if the Native PHY IP core has four channels—logical channel 0 to logical
channel 3—and you want to reconfigure logical channel 3 using the embedded
reconfiguration streamer, you must write to the control register of logical channel 3
using the reconfiguration interface with the appropriate bit settings.
Note: The soft control and status registers at x340 and x341 are enabled when you enable
the embedded reconfiguration streamer in the Native PHY IP core.
Refer to Steps to Perform Dynamic Reconfiguration for a complete list of steps to
perform dynamic reconfiguration using the IP guided reconfiguration flow with
embedded streamer enabled. To perform a PMA reconfiguration such as TX PLL
switching, CGB divider switching, or reference clock switching, use the reconfiguration
flow for special cases described in Steps to Perform Dynamic Reconfiguration.
Table 266. Control and Status Register Memory Map for Embedded Reconfiguration
Streamer in Native PHY IP
Reconfigura
tion
Address
(hex)
Reconfigura
tion Bit
Attribute
Name
Attribute
Description
Bit
Encoding
Transceiver Block Description
340 7 cfg_load Start
streaming
1'b1 Embedded
Reconfiguration
Streamer
Set to 1'b1 to initiate
streaming, self-clearing bit
6 bcast_en Broadcast
enable
1'b1 Embedded
Reconfiguration
Streamer
Set to 1'b1 to broadcast
the same profile to all the
channels
[2:0] cfg_sel Configuratio
n profile
select
Direct
mapped
Embedded
Reconfiguration
Streamer
Binary encoding of the
configuration Profile to
stream
341 0 rcfg_busy Busy Status
bit
1'b1 Embedded
Reconfiguration
Streamer
Bit is set to:
• 1'b1—streaming is in
progress
• 1'b0—streaming is
complete
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
511

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English