Intel Arria 10 User Manual

2.2. Transceiver Design Flow
Figure 19. Transceiver Design Flow
Note: The design examples on the Intel FPGA wiki page provide useful guidance for developing your own design.
However, the content on the Intel FPGA wiki page is not guaranteed by Intel.
Generate PHY IP Core
Connect Transceiver Datapath to MAC IP Core or to a Data Generator / Analyzer
Select PLL IP Core
Generate the Transceiver PHY Reset Controller
or create your own User-Coded Reset Controller
Compile Design
Verify Design Functionality
Generate PLL IP Core
Configure the PHY IP Core
Select PHY IP Core
Configure the PLL IP Core
Connect PHY IP Core to PLL IP Core, Reset Controller, and
connect reconfiguration logic via Avalon-MM interface
Create reconfiguration logic
(if needed)
Make analog parameter settings to I/O pins using the Assignment Editor or updating the Quartus Prime Settings File
Related Information
http://www.alterawiki.com
2.2.1. Select and Instantiate the PHY IP Core
Select the appropriate PHY IP core to implement your protocol.
Refer to the Arria 10 Transceiver Protocols and PHY IP Support section to decide which
PHY IP to select to implement your protocol.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
33

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English