Intel Arria 10 User Manual

Port Direction Clock Domain Description
Note: Intel recommends transmitting Preset
P8 coefficients for Arria 10 receiver to
recover data successfully.
pipe_g3_rxpresethint[(3
N-1):0]
In Asynchronous
This is used to trigger CTLE adaptation in
Phase2 (EP) /Phase 3 (RP) to achieve
receiver Bit Error Rate (BER) that is less than
10
-12
.
Gen3 capable design at Gen1/Gen2 speeds:
This should be set to 3’b000.
Gen3 capable design at Gen3 speed: Refer to
section “PHY IP Core for PCIe (PIPE) Link
Equalization for Gen3 Data Rate” for details
on when to set/reset this port.
pipe_rx_eidleinfersel[(
3N-1):0]
In Asynchronous
When asserted high, the electrical idle state
is inferred instead of being identified using
analog circuitry to detect a device at the
other end of the link. The following encodings
are defined:
3'b0xx: Electrical Idle Inference not required
in current LTSSM state.
3'b100: Absence of COM/SKP OS in 128 ms.
3'b101: Absence of TS1/TS2 OS in 1280 UI
interval for Gen1 or Gen2.
3'b110: Absence of Electrical Idle Exit in
2000 UI interval for Gen1 and 16000 UI
interval for Gen2.
3'b111: Absence of Electrical Idle exit in 128
ms window for Gen1.
Note: Recommended to implement Receiver
Electrical Idle Inference (EII) in FPGA
fabric.
pipe_rate[1:0]
In Asynchronous
The 2-bit encodings defined in the following
list:
2'b00: Gen1 rate (2.5 Gbps)
2'b01: Gen2 rate (5.0 Gbps)
2'b10: Gen3 rate (8.0 Gbps)
pipe_sw_done[1:0]
In N/A
Signal from the Master clock generation
buffer, indicating that the rate switch has
completed. Use this signal for bonding mode
only.
For non-bonded applications, this signal is
internally connected to the local CGB.
pipe_tx_data_valid[(N-1
):0]
In
tx_coreclkin
For Gen3, this signal is deasserted by the
MAC to instruct the PHY to ignore
tx_parallel_data for current clock cycle.
A value of 1'b1 indicates the PHY should use
the data. A value of 0 indicates the PHY
should not use the data.
Active High
PIPE Output to PHY - MAC Layer
rx_parallel_data[31:0],
[15:0], or [7:0]
Out
rx_coreclkin
The RX parallel data driven to the MAC.
For Gen1 this can be 8 or 16 bits. For Gen2
this is 16 bits only. For Gen3 this is 32
bits.Refer to Bit Mappings When the
Simplified Interface is Disabled for more
details.
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
261

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex