Intel Arria 10 User Manual

Port Direction Clock Domain Description
For example, if the MAC connected to PIPE
Gen3x4 has 1bit/lane, then you can use the
following mapping to connect to PIPE:
{pipe_tx_compliance[15:0]= {{4{tx_
compliance _ch3}}, {4{tx_ compliance
_ch2}}, {4{tx_ compliance _ch1}}, {4{tx_
compliance _ch0}}}. Where tx_ compliance
_* is the output signal from MAC.
Active High
pipe_rx_polarity[(N-1):
0]
In Asynchronous
When 1'b1, instructs the PHY layer to invert
the polarity on the received data.
Active High
pipe_powerdown[(2N-1):
0]
In
tx_coreclkin
Requests the PHY to change its power state
to the specified state. The Power States are
encoded as follows:
2'b00: P0 - Normal operation.
2'b01: P0s - Low recovery time, power
saving state.
2'b10: P1 - Longer recovery time, lower
power state .
2'b11: P2 - Lowest power state.
pipe_tx_margin[(3N-1):
0]
In
tx_coreclkin
Transmit V
OD
margin selection. The PHY-MAC
sets the value for this signal based on the
value from the Link Control 2 Register. The
following encodings are defined:
3'b000: Normal operating range
3'b001: Full swing: 800 - 1200 mV; Half
swing: 400 - 700 mV.
3'b010:-3'b011: Reserved.
3'b100-3'b111: Full swing: 200 - 400mV;
Half swing: 100 - 200 mV else reserved.
pipe_tx_swing[(N-1):0]
In
tx_coreclkin
Indicates whether the transceiver is using
Full swing or Half swing voltage as defined by
the pipe_tx_margin.
1'b0-Full swing.
1'b1-Half swing.
pipe_tx_deemph[(N-1):0]
In Asynchronous
Transmit de-emphasis selection. In PCI
Express Gen2 (5 Gbps) mode it selects the
transmitter de-emphasis:
1'b0: –6 dB.
1'b1: –3.5 dB.
pipe_g3_tx_deemph[(18N-
1):0]
In Asynchronous
The pipe_g3_tx_deemph port is used to
select the link partners transmitter de-
emphasis during equalization. The 18 bits
specify the following coefficients:
[5:0]: C
-1
[11:6]: C
0
[17:12]: C
+1
Refer to Preset Mappings to TX De-emphasis
on page 267 for presets to TX de-emphasis
mappings. In Gen3 capable designs, the TX
de-emphasis for Gen2 data rate is always -6
dB. The TX de-emphasis for Gen1 data rate
is always -3.5 dB.
Refer to section 6.6 of Intel PHY Interface for
PCI Express (PIPE) Architecture for more
information.
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
260

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex