Intel Arria 10 - Page 259

Port Direction Clock Domain Description
Refer to Lane Level Encoding in the PCI
Express Base Specification, Rev. 3.0 for a
detailed explanation of data transmission and
reception using 128b/130b encoding and
decoding.
Not used for Gen1 and Gen2 data rates.
Active High
pipe_tx_blk_start[(N-1)
:0]
In
tx_coreclkin
For Gen3, specifies the start block byte
location for TX data in the 128-bit block data.
Used when the interface between the PCS
and PHY-MAC (FPGA Core) is 32 bits.
Not used for Gen1 and Gen2 data rates.
Active High
pipe_tx_elecidle[(4N-1)
:0]
In Asynchronous
Forces the transmit output to electrical idle.
Refer to the Intel PHY Interface for PCI
Express (PIPE) for timing diagrams.
Gen1 - Width of signal is 1 bit/lane.
Gen2 - Width of signal is 2 bits/lane. For
example, if the MAC connected to PIPE
Gen2x4 has 1bit/lane, then you can use the
following mapping to connect to PIPE:
{pipe_tx_elecidle[7:0] =
{{2{tx_elecidle_ch3}},
{2{tx_elecidle_ch2}},{2{tx_elecidle_ch1}},
{2{tx_elecidle_ch0}}} where tx_elecidle_*
is the output signal from MAC.
Gen3 - Width of signal is 4 bits/lane. For
example, if the MAC connected to PIPE
Gen3x4 has 1bit/lane, then you can use the
following mapping to connect to PIPE:
{pipe_tx_elecidle[15:0] =
{{4{tx_elecidle_ch3}},
{4{tx_elecidle_ch2}},{4{tx_elecidle_ch1}},
{4{tx_elecidle_ch0}}} where tx_elecidle_*
is the output signal from MAC.
Active High
pipe_tx_detectrx_loopba
ck [(N-1):0]
In
tx_coreclkin
Instructs the PHY to start a receive detection
operation. After power-up, asserting this
signal starts a loopback operation. Refer to
section 6.4 of the Intel PHY Interface for PCI
Express (PIPE) for a timing diagram.
Active High
pipe_tx_compliance[(4N-
1):0]
In
tx_coreclkin
Asserted for one cycle to set the running
disparity to negative. Used when transmitting
the compliance pattern. Refer to section 6.11
of the Intel PHY Interface for PCI Express
(PIPE) Architecture for more information.
Gen1 - Width of signal is 1 bit/lane.
Gen2 - Width of signal is 2 bits/lane.
For example, if the MAC connected to PIPE
Gen2x4 has 1bit/lane, then you can use the
following mapping to connect to PIPE:
{pipe_tx_compliance[7:0] =
{{2{tx_compliance_ch3}},
{2{tx_compliance _ch2}},
{2{tx_compliance_ch1}}, {2{tx_compliance
_ch0}}}. Where tx_compliance_* is the
output signal from MAC.
Gen3 - Width of signal is 4 bits/lane.
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
259