Intel Arria 10 User Manual

Table 190. Ports for Arria 10 Transceiver Native PHY in PIPE Mode
This section contains the recommended settings for this protocol. Refer to Using the Arria 10 Transceiver
Native PHY IP Core for the full range of parameter settings.
Port Direction Clock Domain Description
Clocks
rx_cdr_refclk0
In N/A
The 100/125 MHz input reference clock
source for the PHY's TX PLL and RX CDR.
tx_serial_clk0/
tx_serial_clk1
In N/A
The high speed serial clock generated by the
PLL.
Note: For Gen3 x1 ONLY tx_serial_clk1
is used.
pipe_hclk_in[0]
In N/A
The 500 MHz clock used for the ASN block.
This clock is generated by the PLL,
configured for Gen1/Gen2.
Note: For Gen3 designs, use from the fPLL
that is used for Gen1/Gen2.
pipe_hclk_out[0]
Out N/A
The 500 MHz clock output provided to the
PHY - MAC interface. The pipe_hclk_out
[0] port can be left floating when you
connect tx_clkout to the MAC clock input.
PIPE Input from PHY - MAC Layer
tx_parallel_data[31:0],
[15:0], or [7:0]
In
tx_coreclkin
The TX parallel data driven from the MAC.
For Gen1 this can be 8 or 16 bits. For Gen2
this is 16 bits. For Gen3 this is 32 bits.
Note: unused_tx_parallel_data should
be tied to '0'.
Active High. Refer to table Bit Mappings when
the Simplified Interface is Disabled for
additional details.
tx_datak[3:0], [1:0], or
[0]
In
tx_coreclkin
The data and control indicator for the
transmitted data.
For Gen1 or Gen2, when 0, indicates that
tx_parallel_data is data, when 1,
indicates that tx_parallel_data is
control.
For Gen3, bit[0] corresponds to
tx_parallel_data[7:0], bit[1]
corresponds to tx_parallel_data[15:8],
and so on.
Active High. Refer to table Bit Mappings when
the Simplified Interface is Disabled for
additional details.
pipe_tx_sync_hdr[(2N-1)
:0]
(43)
In
tx_coreclkin
For Gen3, indicates whether the 130-bit
block transmitted is a Data or Control
Ordered Set Block.
The following encodings are defined:
2'b10: Data block
2'b01: Control Ordered Set Block
This value is read when
pipe_tx_blk_start = 1b'1.
continued...
(43)
N is the number of PCIe channels.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
258

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex