Intel Arria 10 User Manual

Parameter Gen1 PIPE Gen2 PIPE Gen3 PIPE
Number of word alignment patterns to
achieve sync
3 3 3
Number of invalid data words to lose
sync
16 16 16
Number of valid data words to
decrement error count
15 15 15
Enable rx_std_wa_patternalign port
Optional Optional Optional
Enable rx_std_wa_a1a2size port
Off Off Off
Enable rx_std_bitslipboundarysel
port
Optional Optional Optional
Enable rx_bitslip port
Off Off Off
Bit Reversal and Polarity Inversion
Enable TX bit reversal Off Off Off
Enable TX byte reversal Off Off Off
Enable TX polarity inversion Off Off Off
Enable tx_polinv port
Off Off Off
Enable RX bit reversal Off Off Off
Enable rx_std_bitrev_ena port
Off Off Off
Enable RX byte reversal Off Off Off
Enable rx_std_byterev_ena port
Off Off Off
Enable RX polarity inversion Off Off Off
Enable rx_polinv port
Off Off Off
Enable rx_std_signaldetect port
Optional Optional Optional
PCIe Ports
Enable PCIe dynamic datarate switch
ports
Off Enabled Enabled
Enable PCIe pipe_hclk_in and
pipe_hclk_out ports
Enabled Enabled Enabled
Enable PCIe Gen3 analog control ports Off Off Enabled
Enable PCIe electrical idle control and
status ports
Enabled Enabled Enabled
Enable PCIe pipe_rx_polarity port
Enabled Enabled Enabled
Dynamic reconfiguration
Enable dynamic reconfiguration Disabled Disabled Disabled
Note: The signals in the left-most column are automatically mapped to a subset of a 128-bit
tx_parallel_data word when the Simplified Interface is enabled.
Related Information
• How to Place Channels for PIPE Configurations on page 268
• Using the Arria 10 Transceiver Native PHY IP Core on page 45
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
252

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex