Intel Arria 10 - Page 251

Parameter Gen1 PIPE Gen2 PIPE Gen3 PIPE
FPGA Fabric / Standard TX PCS interface
width
8, 16 16 32
FPGA Fabric / Standard RX PCS interface
width
8, 16 16 32
Enable Standard PCS low latency mode Off Off Off
Standard PCS FIFO
TX FIFO mode
low_latency low_latency low_latency
RX FIFO mode
low_latency low_latency low_latency
Enable tx_std_pcfifo_full port
Optional Optional Optional
Enable tx_std_pcfifo_empty port
Optional Optional Optional
Enable rx_std_pcfifo_full port
Optional Optional Optional
Enable rx_std_pcfifo_empty port
Optional Optional Optional
Byte Serializer and Deserializer
TX byte serializer mode Disabled, Serialize x2 Serialize x2 Serialize x4
RX byte deserializer mode Disabled, Serialize x2 Serialize x2 Deserialize x4
8B/10B Encoder and Decoder
Enable TX 8B/10B encoder Enabled Enabled Enabled
Enable TX 8B/10B disparity control Enabled Enabled Enabled
Enable RX 8B/10B decoder Enabled Enabled Enabled
Rate Match FIFO
Rate Match FIFO mode PIPE, PIPE 0ppm PIPE, PIPE 0ppm PIPE, PIPE 0ppm
RX rate match insert / delete -ve pattern
(hex)
0x0002f17c (K28.5/
K28.0/)
0x0002f17c (K28.5/
K28.0/)
0x0002f17c (K28.5/
K28.0/)
RX rate match insert / delete +ve
pattern (hex)
0x000d0e83 (K28.5/
K28.0/)
0x000d0e83 (K28.5/
K28.0/)
0x000d0e83
(K28.5/K28.0/)
Enable rx_std_rmfifo_full port
Optional Optional Optional
Enable rx_std_rmfifo_empty port
Optional Optional Optional
PCI Express Gen 3 rate match FIFO
mode
Bypass Bypass 600
Word Aligner and Bit Slip
Enable TX bit slip Off Off Off
Enable tx_std_bitslipboundarysel
port
Optional Optional Optional
RX word aligner mode
Synchronous State
Machine
Synchronous State
Machine
Synchronous State
Machine
RX word aligner pattern length 10 10 10
RX word aligner pattern (hex)
0x0000 00000000017c (/
K28.5/)
0x0000 00000000017c (/
K28.5/)
0x0000
00000000017c(/
K28.5/)
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
251