Intel Arria 10 User Manual

Table 186. Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - RX
PMA
This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10
Transceiver Native PHY IP Core for the full range of parameter values.
Gen1 PIPE Gen2 PIPE Gen3 PIPE
RX CDR Options
Number of CDR reference clocks 1 1 1
Selected CDR reference clock 0 0 0
Selected CDR reference clock frequency 100, 125 MHz 100, 125 MHz 100, 125 MHz
PPM detector threshold 1000 1000 1000
Equalization
CTLE adaptation mode
Note:
Triggered adaptation mode is
used only for PCIe Gen3.
Manual / Triggered Manual / Triggered Manual / Triggered
DFE adaptation mode Disabled Disabled Disabled
Number of fixed dfe taps NA NA NA
RX PMA Optional Ports
Enable rx_analog_reset_ack port
Optional Optional Optional
Enable rx_pma_clkout port
Optional Optional Optional
Enable rx_pma_div_clkout port
Optional Optional Optional
rx_pma_div_clkout division factor
Optional Optional Optional
Enable rx_pma_clkslip port
Optional Optional Optional
Enable rx_pma_qpipulldn port (QPI)
Off Off Off
Enable rx_is_lockedtodata port
Optional Optional Optional
Enable rx_is_lockedtoref port
Optional Optional Optional
Enable rx_set_locktodata and
rx_set_locktoref ports
Optional Optional Optional
Enable rx_seriallpbken port
Optional Optional Optional
Enable PRBS Verifier Control and Status
ports
Optional Optional Optional
Table 187. Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes -
Standard PCS
This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10
Transceiver Native PHY IP Core for the full range of parameter values.
Parameter
Gen1 PIPE Gen2 PIPE Gen3 PIPE
Standard PCS configurations
Standard PCS / PMA interface width 10 10 10
(42)
continued...
(42)
The PIPE is configured in Gen1/Gen2 during Power Up. Gen3 PCS is configured for PCS/PMA
width of 32.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex