Intel Arria 10 User Manual

5.2.1.1.1. Phase Compensation Mode
In Phase Compensation mode, the TX Core FIFO decouples phase variations between
tx_coreclkin and PCS_clkout_x2(tx). In this mode, read and write of the TX
Core FIFO can be driven by clocks from asynchronous clock sources but must be same
frequency. You can use tx_coreclkin (FPGA fabric clock) or tx_clkout1 (TX
parallel clock) to clock the write side of the TX Core FIFO.
Note: Phase Compensation mode, TX parallel data is valid for every low speed clock cycle,
and tx_enh_data_valid signal should be tied with 1'b1.
Note: Phase Compensation can also be used in double rate transfer mode, where the FPGA
fabric data width is doubled to allow the FPGA fabric clock to run at half rate. The
double rate transfer mode is set in the Native PHY IP Parameter Editor. Refer to the
"Transmitter Data Path Interface Clocking" and "Receiver Data Path Interface Clocking"
sections in the PLLs and Clock Networks chapter for details about the clock
frequencies, when using FIFO single and double rate transfer mode.
Related Information
• Transmitter Data Path Interface Clocking on page 386
• Receiver Data Path Interface Clocking on page 387
5.2.1.1.2. Register Mode
The Register Mode bypasses the FIFO functionality to eliminate the FIFO latency
uncertainty for applications with stringent latency requirements. This is accomplished
by tying the read clock of the FIFO with its write clock.
In Register mode, tx_parallel_data (data), tx_control (indicates whether
tx_parallel_data is a data or control word), and tx_enh_data_valid (data
valid) are registered at the FIFO output.
Note: Intel recommends that you implement a soft FIFO in the FPGA fabric with a minimum
of 32 words under the following conditions:
• When the Enhanced PCS TX FIFO is set to register mode.
• When using the recovered clock to drive the core logic.
• When there is no soft FIFO being generated along with the IP Catalog.
5.2.1.1.3. Interlaken Mode
In Interlaken mode, the TX Core FIFO operates as an elastic buffer. In this mode, you
have additional signals to control the data flow into the FIFO. Therefore, the FIFO
write clock frequency does not have to be the same as the read clock frequency. You
control the writing to the TX Core FIFO with tx_fifo_wr_en by monitoring the FIFO
flags. The goal is to prevent the FIFO from becoming full or empty. On the read side,
read enable is controlled by the Interlaken frame generator.
5.2.1.1.4. Basic Mode
In Basic mode, the TX Core FIFO operates as an elastic buffer, where buffer depths
can vary. This mode allows driving write and read side of TX Core FIFO with different
clock frequencies. Monitor the FIFO flag to control write and read operations. For TX
Core FIFO, assert tx_fifo_wr_en with tx_fifo_pempty signal going low.
5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
Intel
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Arria
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex