Intel Arria 10 User Manual

5.2.1.2. Interlaken Frame Generator
The Interlaken frame generator block takes the data from the TX FIFO and
encapsulates the payload and burst/idle control words from the FPGA fabric with the
framing layer’s control words (synchronization word, scrambler state word, skip word,
and diagnostic word) to form a metaframe. The Native PHY IP Parameter Editor allows
you to set the metaframe length from five 8-byte words to a maximum value of 8192
(64Kbyte words).
Use the same value on frame generator metaframe length for the transmitter and
receiver.
Figure 237. Interlaken Frame Generator
The Interlaken frame generator implements the Interlaken protocol.
Interlaken
Frame
Generator
Synchronization
Scrambler
State Word
Skip Word
Data
Sync Header
Inversion Bit (Place Holder for Bit Inversion Information)
Payload
66 65 64
64-Bit Data
1-Bit Control
66-Bit Blocks
63 66 660 0 Di0
Used for Clock Compensation in a Repeater
Used to Synchronize the Scrambler
Used to Align the Lanes of the Bundle
Provides Per
Lane Error Check
and Optional Status
Message
From TX FIFO
To Interlaken
CRC-32 Generator
5.2.1.3. Interlaken CRC-32 Generator
The Interlaken CRC-32 generator block receives data from the Interlaken frame
generator and calculates the cyclic redundancy check (CRC) code for each block of
data. This CRC code value is stored in the CRC32 field of the diagnostic word. CRC-32
provides a diagnostic tool for each lane. This helps to trace the errors on the interface
back to an individual lane.
The CRC-32 calculation covers most of the metaframe, including the diagnostic word,
except the following:
• Bits [66:64] of each word
• 58-bit scrambler state within the scrambler state word
• 32-bit CRC-32 field within the diagnostic word
5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
464

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex