Intel Arria 10 User Manual

Figure 123. Signals and Ports of Native PHY IP for Basic (Enhanced PCS) and Basic with
KR FEC Configurations
Reconfiguration
Registers
NIOS
Hard Calibration IP
TX PMA
Serializer
tx_serial_data
tx_serial_clk0
(from TX PLL)
rx_cal_busy
tx_cal_busy
rx_serial_data
rx_control[19:0]
rx_cdr_refclk0
rx_is_lockedtodata
rx_is_lockedtoref
rx_parallel_data[127:0]
tx_control[17:0] tx_control[17:0]
tx_digital_resettx_digital_reset
tx_parallel_data[127:0]
reconfig_clk
reconfig_avmm
reconfig_reset
tx_coreclkin
tx_clkout
tx_enh_data_valid
tx_parallel_data[127:0]
tx_coreclkin
tx_clkout
tx_enh_data_valid
RX PMA
TX Enhanced PCS
RX Enhanced PCS
Deserializer
Clock
Generation
Block
rx_cdr_refclk0
CDR
rx_clkout
rx_coreclkin
rx_clkout
rx_coreclkin
rx_analog_reset
tx_analog_reset
rx_digital_resetrx_digital_reset
rx_parallel_data[127:0]
rx_control[19:0]
5. Configure and instantiate the PLL.
6. Create a transceiver reset controller. You can use your own reset controller or use
the Transceiver PHY Reset Controller.
7. Connect the Native PHY IP core to the PLL IP core and the reset controller.
Figure 124. Connection Guidelines for a Basic (Enhanced PCS) Transceiver Design
Reset
Controller
Arria 10 Transceiver
Native PHY
Design
Testbench
32-bit data
(32:32
gearbox ratio)
PLL IP Core
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
292

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex