Intel Arria 10 - Page 410

Figure 198. Mix and Match Design Example
Transceiver Bank
Transceiver Bank
ATX PLL
4 GHz
Transceiver Bank
fPLL, 5.15625 GHz
Transceiver Bank
fPLL
5.15625 GHz
Interlaken 12.5G
1.25G
Interlaken 12.5G
Interlaken 12.5G
Interlaken 12.5G
Interlaken 12.5G
Interlaken 12.5G
Interlaken 12.5G
Interlaken 12.5G
Interlaken 12.5G
Interlaken 12.5G
10GBASE-KR
10GBASE-KR
10GBASE-KR
10GBASE-KR
1.25G
1.25G
1.25G
PCIe Gen 1/2/3 x8
1.25G GbE
1.25G GbE
PCIe Gen 1/2/3 x8
PCIe Gen 1/2/3 x8
PCIe Gen 1/2/3 x8
PCIe Gen 1/2/3 x8
PCIe Gen 1/2/3 x8
PCIe Gen 1/2/3 x8
PCIe Gen 1/2/3 x8
Unused
Unused
Transceiver Bank
ATX PLL
6.25 GHz
MCGB
xN
x6
x1
xN
x6
MCGB
fPLL
2.5 GHz
mcgb_aux_clk0
fPLL, 625 MHz
x1
x1
Interlaken12.5G
10GBASE-KR
1.25G/9.8G/10.3125G
Legend
1.25G GbE
PCIe Gen 1/2/3
Unused channel
PLL Instances
In this example, two ATX PLL instances and five fPLL instances are used. Choose an
appropriate reference clock for each PLL instance. The IP Catalog lists the available
PLLs.
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
410