Intel Arria 10 User Manual

Use the following data rates and configuration settings for PLL IP cores:
• Transceiver PLL Instance 0: ATX PLL with output clock frequency of 6.25 GHz
— Enable the Master CGB and bonding output clocks.
• Transceiver PLL instance 1: fPLL with output clock frequency of 5.1625 GHz
• Transceiver PLL instance 2: fPLL with output clock frequency of 5.1625 GHz
• Transceiver PLL instance 3: fPLL with output clock frequency of 0.625 GHz
— Select the Use as Transceiver PLL option.
• Transceiver PLL instance 4: fPLL with output clock frequency of 2.5 GHz
— Select Enable PCIe* clock output port option.
— Select Use as Transceiver PLL option.
• Set Protocol Mode to PCIe Gen2.
— Select the Use as Core PLL option
• Set the Desired frequency to 500 MHz with a phase shift of 0 ps.
• Transceiver PLL instance 6: ATX PLL with output clock frequency of 4 GHz
— Enable Master CGB and bonding output clocks.
— Select Enable PCIe clock switch interface option.
— Set Number of Auxiliary MCGB Clock Input ports to 1.
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
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Arria
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex