Intel Arria 10 User Manual

Name Value Description
Connect to NBASE-T PHY On, Off Select this option when the external PHY is NBASE-T
compatible.
This parameter is enabled for 1G/2.5G/5G/10G
(USXGMII) modes.
PHY ID (32 bit) 32-bit value An optional 32-bit unique identifier:
• Bits 3 to 24 of the Organizationally Unique Identifier
(OUI) assigned by the IEEE
• 6-bit model number
• 4-bit revision number
If unused, do not change the default value, which is
0x00000000.
Reference clock frequency for
10 GbE (MHz)
322.265625, 644.53125 Specify the frequency of the reference clock for 10GbE.
Selected TX PMA local clock
division factor for 1 GbE
1, 2, 4, 8
This parameter is the local clock division factor in the 1G
mode. It is directly mapped to the Native PHY IP Core
GUI options.
Selected TX PMA local clock
division factor for 2.5 GbE
1, 2
This parameter is the local clock division factor in the
2.5G mode. It is directly mapped to the Native PHY IP
Core GUI options.
Enable Altera Debug Master
Endpoint
On, Off Available in Native PHY and TX PLL IP parameter editors.
When enabled, the Altera Debug Master Endpoint
(ADME) is instantiated and has access to the Avalon-MM
interface of the Native PHY. You can access certain test
and debug functions using System Console with the
ADME. Refer to the Embedded Debug Features section
for more details about ADME.
Enable capability registers On, Off Available in Native PHY and TX PLL IP parameter editors.
Enables capability registers. These registers provide
high-level information about the transceiver channel's /
PLL's configuration.
Set user-defined IP identifier User-specified Available in Native PHY and TX PLL IP parameter editors.
Sets a user-defined numeric identifier that can be read
from the user_identifier offset when the capability
registers are enabled.
Enable control and status
registers
On, Off Available in Native PHY and TX PLL IP parameter editors.
Enables soft registers for reading status signals and
writing control signals on the PHY /PLL interface through
the ADME or reconfiguration interface.
Enable PRBS soft
accumulators
On, Off Available in Native PHY IP parameter editor only.
Enables soft logic to perform PRBS bit and error
accumulation when using the hard PRBS generator and
checker.
Related Information
Embedded Debug Features on page 544
2.6.5.2.2. Timing Constraints
Constrain the PHY based on the fastest speed. For example, if you configure the PHY
as 1G/2.5G, constrain it based on 2.5G.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
202

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex