Intel Arria 10 User Manual

Figure 249. IDLE Word Deletion
This figure shows the deletion of IDLE words from the receiver data stream.
00000000000004ADh 00000000000004AEh
0707070707FD0000h 000000FB07070707h
00000000000004ADh 00000000000004AEh
0707070707FD0000h
AAAAAAAA000000FBh
Idle Deleted
Before Deletion
After Deletion
rx_parallel_data[79:0]
rx_parallel_data[79:0]
Figure 250. OS Word Deletion
This figure shows the deletion of Ordered set words in the receiver data stream.
OS Deleted
Before Deletion
After Deletion
FD000000000004AEh 000000FBDDDDDD9Ch AAAAAAAA00000000h 00000000AAAAAAAAh
FD000000000004AEh DDDDDD9CDDDDDD9Ch 00000000000000FBh AAAAAAAAAAAAAAAAh
rx_parallel_data[79:0]
rx_parallel_data[79:0]
Idle Insertion
Idle insertion occurs in groups of 8 Idles when the rx_enh_fifo_pempty flag is
deasserted. Idles can be inserted following Idles or OS. Idles are inserted in groups of
8 bytes. Data shifting is not necessary. There is a synchronous status
rx_enh_fifo_insert signal that is attached to the 8-byte Idles being inserted.
Table 258. Cases Where Two Idle Words are Inserted
In this table X=don’t care, S=start, OS=order set, I-DS=idle in data stream, and I-In=idle inserted. In cases 3
and 4, the Idles are inserted between the LW and UW.
Case
Word Input Output
1 UW I-DS I-DS I-In
LW X X I-In
2 UW OS OS I-In
LW X X I-In
3 UW S I-In S
LW I-DS I-DS I-In
4 UW S I-In S
LW OS OS I-In
Figure 251. IDLE Word Insertion
This figure shows the insertion of IDLE words in the receiver data stream.
Idle Inserted
Before Insertion
After Insertion
FD000000000004AEh BBBBBB9CDDDDDD9Ch 0707070707070707h 00000000000000FBh
FD000000000004AEh BBBBBB9CDDDDDD9Ch 00000000000000FBh AAAAAAAAAAAAAAAAh
rx_parallel_data[79:0]
rx_parallel_data[79:0]
5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
478

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex