Intel Arria 10 User Manual

Figure 248. RX FIFO as Interlaken Deskew FIFO
User
Deskew
FSM
FPGA Fabric Interface
rx_enh_fifo_align_clr
rx_enh_fifo_rd_en
rx_enh_fifo_pempty
rx_enh_fifo_pfull
RX FIFO
5.2.2.10.4. 10GBASE-R Mode
In 10GBASE-R mode, the RX FIFO operates as a clock compensation FIFO. When the
block synchronizer achieves block lock, data is sent through the FIFO. Idle ordered
sets (OS) are deleted and Idles are inserted to compensate for the clock difference
between the RX low speed parallel clock and the FPGA fabric clock (±100 ppm for a
maximum packet length of 64,000 bytes).
Idle OS Deletion
Deletion of Idles occurs in groups of four OS (when there are two consecutive OS)
until the rx_enh_fifo_pfull flag deasserts. Every word—consisting of a lower word
(LW) and an upper word (UW)—is checked for whether it can be deleted by looking at
both the current and previous words.
For example, the current LW can be deleted if it is Idle and the previous UW is not a
Terminate.
Table 257. Conditions Under Which a Word Can be Deleted
In this table X=don’t care, T=Terminate, I=Idle, and OS=order set.
Deletable
Case Word Previous Current Output
Lower Word 1 UW !T X !T X
LW X I X X
2 UW OS X OS X
LW X OS X X
Upper Word 1 UW X I X X
LW X !T X !T
2 UW X OS X X
LW X OS X OS
If only one word is deleted, data shifting is necessary because the datapath is two
words wide. After two words have been deleted, the FIFO stops writing for one cycle
and a synchronous flag (rx_control[8]) appears on the next block of 8-byte data.
There is also an asynchronous status signal rx_enh_fifo_del, which does not go
through the FIFO.
5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
Intel
®
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex