Intel Arria 10 User Manual

When phase compensation is used in double-width mode, the FPGA data width is
doubled to allow the FPGA fabric clock to run at half rate, similar to the TX FIFO phase
compensation in double-width mode.
Depth of RX FIFO is constant in this mode, therefore RX FIFO flag status can be
ignored. You can tie tx_enh_data_valid with one.
5.2.2.10.2. Register Mode
The Register Mode bypasses the FIFO functionality to eliminate the FIFO latency
uncertainty for applications with stringent latency requirements. This is accomplished
by tying the read clock of the FIFO with its write clock.
In Register mode, rx_parallel_data (data), rx_control indicates whether
rx_parallel_data is a data or control word, and rx_enh_data_valid (data valid)
are registered at the FIFO output. The RX FIFO in register mode has one register
stage or one parallel clock latency.
Note: Intel recommends that you implement a soft FIFO in the FPGA fabric with minimum of
32 words under the following conditions:
• When the Enhanced PCS RX FIFO is set to register mode.
• When using the recovered clock to drive the core logics.
• When there is no soft FIFO being generated along with the IP Catalog.
5.2.2.10.3. Interlaken Mode
In Interlaken mode, the RX FIFO operates as an Interlaken deskew FIFO. To
implement the deskew process, implement an FSM that controls the FIFO operation
based on available FPGA input and output flags.
For example, after frame lock is achieved, data is written after the first alignment
word (SYNC word) is found on that channel. As a result, rx_enh_fifo_pempty (FIFO
partially empty flag ) of that channel goes low. You must monitor the
rx_enh_fifo_pempty and rx_enh_fifo_pfull flags of all channels. If
rx_enh_fifo_pempty flags from all channels deassert before any
rx_enh_fifo_pfull flag asserts, which implies alignment word has been found on
all lanes of the link, you start reading from all the FIFOs by asserting
rx_enh_fifo_rd_en. Otherwise, if a rx_enh_fifo_pfull flag from any channel
goes high before a rx_enh_fifo_pempty flag deassertion on all channels, you must
reset the FIFO by toggling the rx_enh_fifo_align_clr signal and repeating the
process.
5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
Intel
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Arria
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex