Intel Arria 10 User Manual

5.2.2.8. 10GBASE-R Bit-Error Rate (BER) Checker
The 10GBASE-R BER checker block is designed in accordance with the 10GBASE-R
protocol specification as described in IEEE 802.3-2008 clause-49. After block lock
synchronization is achieved, the BER checker starts to count the number of invalid
synchronization headers within a 125-μs period. If more than 16 invalid
synchronization headers are observed in a 125-μs period, the BER checker provides
the status signal rx_enh_highber to the FPGA fabric, indicating a high bit error rate
condition.
When the optional control input rx_enh_highber_clr_cnt is asserted, the internal
counter for the number of times the BER state machine has entered the
"BER_BAD_SH" state is cleared.
When the optional control input rx_enh_clr_errblk_count is asserted, the
internal counter for the number of times the RX state machine has entered the "RX_E"
state for the 10GBASE-R protocol is cleared. In modes where the FEC block in
enabled, the assertion of this signal resets the status counters within the RX FEC
block.
Note: The 10GBASE-R BER checker is available to implement the 10GBASE-R protocol.
5.2.2.9. Interlaken CRC-32 Checker
The Interlaken CRC-32 checker verifies that the data transmitted has not been
corrupted between the transmit PCS and the receive PCS. The CRC-32 checker
calculates the 32-bit CRC for the received data and compares it against the CRC value
that is transmitted within the diagnostic word. rx_enh_crc32_err (CRC error signal)
is sent to the FPGA fabric.
5.2.2.10. Enhanced PCS RX FIFO
The Enhanced PCS RX FIFO is designed to compensate for the phase, clock, or phase
and clock difference between the receiver channel PCS and the FPGA fabric. It can
operate as a phase-compensation, clock-compensation, elastic buffer, or a deskew
FIFO in Interlaken mode. The RX FIFO has a width of 74 bits and a depth of 32 words
for all protocols.
The RX FIFO supports the following modes:
• Phase Compensation mode
• Register mode
• Interlaken mode (deskew FIFO)
• 10GBASE-R mode (clock compensation FIFO)
• Basic mode (elastic buffer FIFO)
5.2.2.10.1. Phase Compensation Mode
The RX FIFO compensates for the phase difference between the read clock and write
clocks. rx_clkout (RX parallel low-speed clock) clocks the write side of the RX FIFO.
rx_coreclkin (FPGA fabric clock) or rx_clkout clocks the read side of the RX
FIFO.
5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex