Intel Arria 10 User Manual

Figure 215. Transceiver PHY Reset Controller System Diagram
(user-coded
Reset Controller
Transceiver PHY Instance
tx_analogreset
tx_digitalreset
rx_analogreset
rx_digitalreset
rx_cal_busy
rx_is_lockedtoref
rx_is_lockedtodata
Transmit
PLL
pll_powerdown
pll_locked
clock
reset
Receiver
PCS
Receiver
PMA
Transmitter
PCS
Transmitter
PMA
or Intel IP)
tx_analogreset_ack
rx_analogreset_ack
reset_req_0
reset_out_0
reset_req_1
reset_out_1
tre_reset_req
tre_reset_in tre_reset_req
tre_reset_in
Transceiver Reset Sequencer Inferred Block
clk_usrpin
Optional
tx_ready rx_ready
Status Signals
tx_cal_busy (1)
pll_tx_cal_busy
pll_cal_busy (1)
You can logical OR the pll_cal_busy and tx_cal_busy signals.
pll_tx_cal_busy connects to the controller’s tx_cal_busy input port.
Note:
(1)
(2)
(2) The ports are inputs for user logic that implement Model 2. The ports can be used as status monitoring for Model 1 implementation. .
(2)
4. Resetting Transceiver Channels
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
434

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex