Intel Arria 10 User Manual

There are two ways to check who has the access to the internal configuration bus:
•
Use reconfig_waitrequest
• Use capability registers
The Native PHY IP core and PLL default setting is to use reconfig_waitrequest.
When PreSICE controls the internal configuration bus, the reconfig_waitrequest
from the internal configuration bus is high. When user access is granted, the
reconfig_waitrequest from the internal configuration bus goes low. At the Avalon-
MM reconfiguration interface, the reconfig_waitrequest can come from a few
places inside Native PHY IP core. For example, it can come from the internal
configuration bus, streamer, and so on. They are bundled together and become single
reconfig_waitrequest at the Avalon-MM reconfiguration interface. The
reconfig_address determines which reconfig_waitrequest to show at the
Avalon-MM reconfiguration interface. After you return the internal configuration bus to
PreSICE, the reconfig_waitrequest from the internal configuration bus is high. If
you set the reconfig_address to the streamer offset address at the Avalon-MM
reconfiguration interface during calibration, the reconfig_waitrequest can be low
before calibration is finished. If you keep the reconfig_address the same as the
internal configuration bus offset address during calibration, the
reconfig_waitrequest at the Avalon-MM reconfiguration interface is high until
PreSICE returns the internal configuration bus to you. It is important to keep
reconfig_address static during calibration.
To use capability registers to check bus arbitration, you do the following to generate
the IP:
1. Select Enable dynamic reconfiguration from the Dynamic Reconfiguration
tab.
2. Select both the Separate reconfig_waitrequest from the status of AVMM
arbitration with PreSICE and Enable control and status registers options.
You can read the capability register 0x281[2] to check who is controlling the channel
access, and read the capability register 0x280[2] to check who is controlling the PLL
access. When Separate reconfig_waitrequest from the status of AVMM
arbitration with PreSICE and Enable control and status registers are enabled,
the reconfig_waitrequest is not asserted high when PreSICE controls the internal
configuration bus.
To return the internal configuration bus to PreSICE:
• In order to trigger user re-calibration:
— Write 0x01 to offset address 0x000 [7:0], user re-calibration has to request
through offset address 0x100.
• In order to trigger DFE adaptation:
— Write 0x03 to offset address 0x000 [7:0], DFE adaptation triggering has to
enable through 0x100[6].
• If you no longer need to use the internal reconfiguration bus:
— Write 0x03 to offset address 0x000 [7:0].
7. Calibration
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
568

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English