Intel Arria 10 - Page 270

Figure 110. x4 Configuration
The figure below shows an alternate way of placing 4 bonded channels. In this case, the logical PCS Master
Channel number 2 must be specified as Physical channel 4.
CH5
CH4
CH3
CH2
CH1
CH0
CH5
CH4
CH3
CH2
CH1
CH0
Data CH
fPLL
ATX
PLL
fPLL
ATX
PLL
fPLL
ATX
PLL
fPLL
ATX
PLL
Logical
Channel
Physical
Channel
0
1
Transceiver bank
Transceiver bank
2
3
Data CH
Master
CGB
Master
CGB
Master CH
Master
CGB
Master
CGB
Data CH
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
270