Intel Arria 10 User Manual

Figure 111. x8 Configuration
For x8 configurations, Intel recommends you choose a master channel that is a maximum of four channels
away from the farthest slave channel.
CH5
CH4
CH3
CH2
CH1
CH0
CH5
CH4
CH3
CH2
CH1
CH0
Master CH
Data CH
fPLL
ATX
PLL
fPLL
ATX
PLL
fPLL
ATX
PLL
fPLL
ATX
PLL
Logical
Channel
Physical
Channel
0
1
Transceiver bank
Transceiver bank
2
3
Data CH
Data CH
4
5
6
7
Data CH
Data CH
Data CH
Data CH
Master
CGB
Master
CGB
Master
CGB
Master
CGB
Note: The physical channel 0 aligns with logical channel 0. The logical PCS master channel 4
is specified as Physical channel 4.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
271

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex