Intel Arria 10 User Manual

Figure 112. x4 Alternate Configuration
The figure below shows an alternate way of placing 4 bonded channels. In this case, the logical PCS Master
Channel number 2 must be specified as Physical channel 1.
CH5
CH4
CH3
CH2
CH1
CH0
CH5
CH4
CH3
CH2
CH1
CH0
Master CH
fPLL
ATX
PLL
fPLL
ATX
PLL
fPLL
ATX
PLL
fPLL
ATX
PLL
Logical
Channel
Physical
Channel
0
1
Transceiver bank
2
3
Data CH
Data CH
Master
CGB
Master
CGB
Transceiver bank
Data CH
Master
CGB
Master
CGB
As indicated in the figures above, the fitter picks either physical CH1 or CH4 as the
PCS master in bonded configurations for PIPE.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
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®
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex