Intel Arria 10 User Manual

a. Access the internal configuration bus by writing 0x2 to offset address
0x0[7:0].
b.
Wait for reconfig_waitrequest to deassert (logic low), or wait until
capability register of PreSICE Avalon-MM interface control 0x280[2]=0x0.
c. Read-Modify-Write 0x1 to the offset address 0x100[1] of the fPLL.
d. Release the internal configuration bus to PreSICE to perform recalibration by
writing 0x1 to offset address 0x0[7:0].
e.
Periodically check the *cal_busy output signals or read the capability
registers 0x280[1] to check *cal_busy status until calibration is complete.
If you are recalibrating your fPLL and have ATX PLL used on the same side of the
device, follow the fPLL-to-ATX PLL spacing guideline as stated in the "Transmit
PLLs Spacing Guideline when using ATX PLLs and fPLLs" chapter.
3. Perform the PMA user recalibration process:
a. Request access to the internal configuration bus by writing 0x2 to offset
address 0x0[7:0].
b.
Wait for reconfig_waitrequest to deassert (logic low), or wait until
capability register of PreSICE Avalon-MM interface control 0x281[2]=0x0.
c. Configure the PMA calibration enable register 0x100. You must set 0x0 to
0x100[6] to enable any calibration.
• Read-Modify-Write 0x1 to 0x100[1] to start PMA RX calibration.
• Read-Modify-Write 0x1 to 0x100[5] to start PMA TX calibration.
d. Do Read-Modify-Write on the rate switch flag register if you switched rates
with a different CDR bandwidth setting.
e.
Do Read-Modify-Write on 0x281[5:4] to disable/enable rx_cal_busy and
tx_cal_busy.
•
To enable rx_cal_busy, write 0x1 to 0x281[5].
•
To disable rx_cal_busy, write 0x0 to 0x281[5].
•
To enable tx_cal_busy, write 0x1 to 0x281[4].
•
To disable tx_cal_busy, write 0x0 to 0x281[4].
f. Release the internal configuration bus to PreSICE to perform recalibration by
writing 0x1 to offset address 0x0[7:0].
g.
Perform a loop to check the tx_cal_busy and rx_cal_busy output signals
or read the capability registers 0x281[1:0] to check *cal_busy status until
calibration is complete.
Related Information
Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs on page 349
7. Calibration
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex