Intel Arria 10 User Manual

Signal Name Direction Clock Domain Description
•
reset is asserted
•
rx_analogreset is asserted
•
rx_cal_busy is asserted
•
rx_is_lockedtodata is deasserted and
rx_manual is deasserted
When all of these conditions are false, the reset
counter begins its countdown for deassertion of
rx_digitalreset.
rx_analogreset
[<n>-1:0]
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
Analog reset for RX. When asserted, resets the RX CDR
and the RX PMA blocks of the transceiver PHY. This
signal is asserted when any of the following conditions
is true:
•
reset is asserted
•
rx_cal_busy is asserted
The width of this signal depends on the number of
channels.
rx_ready[<n>-1:0]
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
Status signal to indicate when the RX reset sequence is
complete. This signal is deasserted while the RX reset
is active. It is asserted a few clock cycles after the
deassertion of rx_digitalreset. Some protocol
implementations may require you to monitor this signal
prior to sending data. The width of this signal depends
on the number of RX channels.
pll_powerdown[<p>-1:0
]
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
Asserted to power down a transceiver PLL circuit. When
asserted, the selected TX PLL is reset.
Usage Examples for pll_select
•
If a single channel can switch between three TX PLLs, the pll_select signal
indicates which one of the selected three TX PLL's pll_locked signal is used to
communicate the PLL lock status to the TX reset sequence. In this case, to select
the 3-bits wide pll_locked port, the pll_select port is 2-bits wide.
• If three channels are instantiated with three TX PLLs and with a separate TX reset
sequence per channel, the pll_select field is 6-bits wide (2-bits per channel).
In this case, pll_select [1:0] represents channel 0, pll_select[3:2]
represents channel 1, and pll_select[5:4] represents channel 2. For each
channel, a separate pll_locked signal indicates the PLL lock status.
• If three channels are instantiated with three TX PLLs and with a single TX reset
sequence for all three channels, then pll_select field is 2-bits wide. In this
case, the same pll_locked signal indicates the PLL lock status for all three
channels.
•
If one channel is instantiated with one TX PLL, pll_select field is 1-bit wide.
Connect pll_select to logic 0.
• If three channels are instantiated with only one TX PLL and with a separate TX
reset sequence per channel, the pll_select field is 3-bits wide. In this case,
pll_select should be set to 0 since there is only one TX PLL available.
4. Resetting Transceiver Channels
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
440

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English