Intel Arria 10 User Manual

Signal Name Direction Clock Domain Description
logic does not automatically respond to deassertion of
the pll_locked signal. However, the initial
tx_digitalreset sequence still requires a one-time
rising edge on pll_locked before proceeding. When
deasserted, the associated tx_digitalreset
controller automatically begins its reset sequence
whenever the selected pll_locked signal is
deasserted.
rx_manual[<n> -1:0]
Input Asynchronous
This optional signal places rx_digitalreset logic
controller under automatic or manual control. In
manual mode, the rx_digitalreset controller does
not respond to the assertion or deassertion of the
rx_is_lockedtodata signal. The
rx_digitalreset controller asserts rx_ready when
the rx_is_lockedtodata signal is asserted.
clock
Input N/A A free running system clock input to the Transceiver
PHY Reset Controller from which all internal logic is
driven. If a free running clock is not available, hold
reset until the system clock is stable.
reset
Input Asynchronous Asynchronous reset input to the Transceiver PHY Reset
Controller. When asserted, all configured reset outputs
are asserted. Holding the reset input signal asserted
holds all other reset outputs asserted. An option is
available to synchronize with the system clock. In
synchronous mode, the reset signal needs to stay
asserted for at least (2) clock cycles by default.
tx_digitalreset[<n>-1
:0]
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
Digital reset for TX channels. The width of this signal
depends on the number of TX channels. This signal is
asserted when any of the following conditions is true:
•
reset is asserted
•
pll_powerdown is asserted
•
pll_cal_busy is asserted
•
tx_cal_busy is asserted
•
PLL has not reached the initial lock (pll_locked
deasserted)
•
pll_locked is deasserted and tx_manual is
deasserted
When all of these conditions are false, the reset
counter begins its countdown for deassertion of
tx_digitalreset.
tx_analogreset[<n>-1:
0]
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
Analog reset for TX channels. The width of this signal
depends on the number of TX channels. This signal is
asserted when reset is asserted.
This signal follows pll_powerdown, which is
deasserted after pll_locked goes high.
tx_ready[<n>-1:0]
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
Status signal to indicate when the TX reset sequence is
complete. This signal is deasserted while the TX reset
is active. It is asserted a few clock cycles after the
deassertion of tx_digitalreset. Some protocol
implementations may require you to monitor this signal
prior to sending data. The width of this signal depends
on the number of TX channels.
rx_digitalreset[<n>
-1:0]
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
Digital reset for RX. The width of this signal depends
on the number of channels. This signal is asserted
when any of the following conditions is true:
continued...
4. Resetting Transceiver Channels
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
439

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English