Intel Arria 10 User Manual

Figure 216. Transceiver PHY Reset Controller IP Core Top-Level Signals
Generating the IP core creates signals and ports based on your parameter settings.
pll_locked[<p>–1:0]
pll_select[<p*n>–1:0] (1)
tx_cal_busy[<n>–1:0]
rx_cal_busy[<n>–1:0]
rx_is_lockedtodata[<n>–1:0]
tx_manual[<n>–1:0]
rx_manual[<n>–1:0]
clock
reset
Transceiver PHY Reset Controller Top-Level Signals
tx_digitalreset[<n>–1:0]
tx_analogreset[<n>–1:0]
tx_ready[<n>–1:0]
rx_digitalreset[<n>–1:0]
rx_analogreset[<n>–1:0]
rx_ready[<n>–1:0]
pll_powerdown[<p>–1:0]
PLL and
Calibration
Status
PLL Powerdown
TX and RX
Resets and Status
Clock
and Reset
PLL
Control
Note:
(1) n=1 for pll_select signal width when a single TX reset sequence is used for all channels.
Note: PLL control is available when you enable the Expose Port parameter.
Table 248. Top-Level Signals
This table describes the signals in the above figure in the order that they are shown in the figure.
Signal Name Direction Clock Domain Description
pll_locked[<p>-1:0]
Input Asynchronous Provides the PLL locked status input from each PLL.
When asserted, indicates that the TX PLL is locked.
When deasserted, the PLL is not locked. There is one
signal per PLL.
pll_select[<p*n>-1:0]
Input Synchronous to the
Transceiver PHY Reset
Controller input clock.
Set to zero when not
using multiple PLLs.
When you select Use separate TX reset per
channel, this bus provides enough inputs to specify an
index for each pll_locked signal to listen to for each
channel. When Use separate TX reset per channel
is disabled, the pll_select signal is used for all
channels.
n=1 when a single TX reset sequence is used for all
channels.
tx_cal_busy[<n> -1:0]
Input Asynchronous This is the calibration status signal that results from
the logical OR of pll_cal_busy and tx_cal_busy
signals. The signal goes high when either the TX PLL or
Transceiver PHY initial calibration is active. It is not
asserted if you manually re-trigger the calibration IP.
The signal goes low when calibration is completed. This
signal gates the TX reset sequence. The width of this
signals depends on the number of TX channels.
rx_cal_busy[<n> -1:0]
Input Asynchronous This is calibration status signal from the Transceiver
PHY IP core. When asserted, the initial calibration is
active. When deasserted, calibration has completed.
This signal gates the RX reset sequence. The width of
this signals depends on the number of RX channels.
rx_is_lockedtodata[<n
>-1:0]
Input Synchronous to CDR
Provides the rx_is_lockedtodata status from each
RX CDR. When asserted, indicates that a particular RX
CDR is ready to receive input data. If you do not
choose separate controls for the RX channels, these
inputs are ANDed together internally to provide a
single status signal.
tx_manual[<n>-1:0]
Input Asynchronous
This optional signal places tx_digitalreset
controller under automatic or manual control. When
asserted, the associated tx_digitalreset controller
continued...
4. Resetting Transceiver Channels
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
438

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex