Intel Arria 10 User Manual

Table 178. XAUI PHY IP Core Registers
Word
Addr
Bits R/W Register Name Description
Reset Control Registers–Automatic Reset Controller
0x041 [31:0] RW
reset_ch_bitmask
Bit mask for reset registers at addresses 0x042 and
0x044. The default value is all 1s. You can reset
channel <n> when bit<n> = 1.
0x042 [1:0] W
reset_control(write)
Writing a 1 to bit 0 initiates a TX digital reset using
the reset controller module. The reset affects
channels enabled in the reset_ch_bitmask. Writing
a 1 to bit 1 initiates a RX digital reset of channels
enabled in the reset_ch_bitmask. This bit self-
clears.
R
reset_status(read)
Reading bit 0 returns the status of the reset controller
TX ready bit. Reading bit 1 returns the status of the
reset controller RX ready bit. This bit self-clears.
Reset Controls –Manual Mode
0x044 [31:4,0
]
RW Reserved It is safe to write 0s to reserved bits.
[1] RW
reset_tx_digital
Writing a 1 causes the internal TX digital reset signal
to be asserted, resetting all channels enabled in
reset_ch_bitmask. You must write a 0 to clear the
reset condition.
[2] RW
reset_rx_analog
Writing a 1 causes the internal RX analog reset signal
to be asserted, resetting the RX analog logic of all
channels enabled in reset_ch_bitmask. You must
write a 0 to clear the reset condition.
[3] RW
reset_rx_digital
Writing a 1 causes the RX digital reset signal to be
asserted, resetting the RX digital channels enabled in
reset_ch_bitmask. You must write a 0 to clear the
reset condition.
PMA Control and Status Registers
0x061 [31:0] RW
phy_serial_loopback Writing a 1 to channel <n> puts channel <n> in
serial loopback mode. For information about pre- or
post-CDR serial loopback modes, refer to Loopback
Modes.
0x064 [31:0] RW
pma_rx_set_locktodata
When set, programs the RX CDR PLL to lock to the
incoming data. Bit <n> corresponds to channel <n>.
0x065 [31:0] RW
pma_rx_set_locktoref
When set, programs the RX CDR PLL to lock to the
reference clock. Bit <n> corresponds to channel <n>.
0x066 [31:0] RO
pma_rx_is_lockedtodata
When asserted, indicates that the RX CDR PLL is
locked to the RX data, and that the RX CDR has
changed from LTR to LTD mode. Bit <n> corresponds
to channel <n>.
0x067 [31:0] RO
pma_rx_is_lockedtoref
When asserted, indicates that the RX CDR PLL is
locked to the reference clock. Bit <n> corresponds to
channel <n>.
XAUI PCS
0x084 [31:16] N/A Reserved N/A
[15:8] R Reserved N/A
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
227

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English