Intel Arria 10 User Manual

Phase Frequency Detector (PFD)
The reference clock(refclk) signal at the output of the N counter block and the
feedback clock (fbclk) signal at the output of the M counter block are supplied as
inputs to the PFD. The output of the PFD is proportional to the phase difference
between the refclk and fbclk inputs. It is used to align the refclk signal at the
output of the N counter to the feedback clock (fbclk) signal. The PFD generates an
"Up" signal when the reference clock's falling edge occurs before the feedback clock's
falling edge. Conversely, the PFD generates a "Down" signal when the feedback clock's
falling edge occurs before the reference clock's falling edge.
Charge Pump and Loop Filter
The PFD output is used by the charge pump and loop filter (CP and LF) to generate a
control voltage for the VCO. The charge pump translates the "Up" or "Down" pulses
from the PFD into current pulses. The current pulses are filtered through a low pass
filter into a control voltage that drives the VCO frequency. The charge pump, loop
filter, and VCO settings determine the bandwidth of the ATX PLL.
Lock Detector
The lock detector block indicates when the reference clock and the feedback clock are
phase aligned. The lock detector generates an active high pll_locked signal to
indicate that the PLL is locked to its input reference clock.
Voltage Controlled Oscillator
The voltage controlled oscillator (VCO) used in the ATX PLL is LC tank based. The
output of charge pump and loop filter serves as an input to the VCO. The output
frequency of the VCO depends on the input control voltage. The output frequency is
adjusted based on the output voltage of the charge pump and loop filter.
L Counter
The L counter divides the differential clocks generated by the ATX PLL. The L counter
is not in the feedback path of the PLL.
M Counter
The M counter's output is the same frequency as the N counter's output. The VCO
frequency is governed by the equation:
VCO freq = 2 * M * input reference clock/N
An additional divider divides the high speed serial clock output of the VCO by 2 before
it reaches the M counter.
The M counter supports division factors in a continuous range from 8 to 127 in integer
frequency synthesis mode and 11 to 123 in fractional mode.
Delta Sigma Modulator
The fractional mode is only supported when the ATX PLL is configured as a cascade
source for OTN and SDI protocols. The delta sigma modulator is used in fractional
mode. It modulates the M counter divide value over time so that the PLL can perform
fractional frequency synthesis. In fractional mode, the M value is as follows: .
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
352

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex