Parameter Gen1 PIPE Gen2 PIPE Gen3 PIPE (For Gen3
speed)
Number of auxiliary MCGB clock input
ports
N/A for x1
0 for x2, x4, x8
N/A for x1
0 for x2, x4, x8
N/A for x1
1 for x2, x4, x8
MCGB input clock frequency 1250 MHz 2500 MHz 4000 MHz
MCGB output data rate 2500 Mbps 5000 Mbps 8000 Mbps
Bonding
Enable bonding clock output ports N/A for x1
Enable for x2, x4, x8
N/A for x1
Enable for x2, x4, x8
N/A for x1
Enable for x2, x4, x8
Enable feedback compensation bonding N/A for x1 design
Disable for x2, x4, x8
N/A for x1 design
Disable for x2, x4, x8
Disable for x1
Disable for x2, x4, x8
PMA interface width N/A for x1 design
10 for x2, x4, x8
N/A for x1 design
10 for x2, x4, x8
N/A for x1
10 for x2, x4, x8
Dynamic Reconfiguration
Enable dynamic reconfiguration Disable Disable Disable
Enable Altera Debug Master Endpoint Disable Disable Disable
Separate avmm_busy from
reconfig_waitrequest
N/A N/A N/A
Optional Reconfiguration Logic
Enable capability registers N/A N/A N/A
Set user-defined IP identifier N/A N/A N/A
Enable control and status registers N/A N/A N/A
Configuration Files
Configuration file prefix N/A N/A N/A
Generate SystemVerilog package file N/A N/A N/A
Generate C Header file N/A N/A N/A
Generate MIF (Memory Initialize file) N/A N/A N/A
Generation Options
Generate parameter documentation file Enable Enable Enable
Related Information
Using the Arria 10 Transceiver Native PHY IP Core on page 45
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
256