Document
Version
Changes
Made the following changes to the Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 section:
• Added description about the RX FIFO and TX FIFO in the "GbE with IEEE 1588v2" section.
•
Added a note to the pll_powerdown signal in the "Connection Guidelines for a GbE/GbE with IEEE
1588v2 PHY Design" figure.
• Updated the parameter descriptions for in the "Standard PCS Parameters" table.
Made the following changes to the XAUI PHY IP Core section:
•
Added further description to the rx_channelaligned signal in the "Optional Control and Status
Signals—Soft IP Implementation" table.
Made the following changes to the Using the Arria 10 Transceiver Native PHY IP Core section:
•
Added "Synchronous to rx_clkout" for rx_std_wa_patternalign[<n>-1:0] in the clock
domain column in Word Aligner and Bitslip table.
• Added "Unused Transceiver Channels" section.
Made the following changes to the CPRI section:
• New table "Interface Width Options for 10.1376 Gbps and 12.16512 Gbps Data Rates" added.
• Supported data rates updated for TX PLLs.
• Data rate values updated in table "General and Datapath Options".
Made the following changes to the PCI Express section:
• Added PIPE Interface width number in the Port column in table "Ports for Arria 10 Transceiver
Native PHY in PIPE Mode".
2016.05.02 Made the following changes to the 10GBASE-KR PHY IP Core section:
• Updated the version and release date in the "10GBASE-KR PHY Release Information" table.
• Changed the definitions and parameters in the "General Options Parameters" table.
• Added the "Speed Detection Parameters" table.
• Added and removed parameters in the "Auto Negotiation and Link Training Settings" table.
• Removed parameter from the "10GBASE-R Parameters" table.
• Changed descriptions in the "10GBASE-KR Register Definitions" table for 0x4B0 and 0x4D0.
• Added signals to the "Control and Status Signals" table.
• Added a new bit field for 0x4D1 in the "10GBASE-KR Register Definitions" table.
• Changed the default value for INITPOSTVAL Init Post tap Value in the "10GBASE-KR Optional
Parameters" table.
Made the following changes to the 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core section:
• Changed the "Block Diagram of the PHY IP Core" figure.
• Updated the version and release date in the "PHY Release Information" table.
• Updated the "Resource Utilization" table.
• Updated the "PHY Features" table.
• Changed the "1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core Parameters" table.
• Added signals to the "PHY Interface Signals" figure.
• Added descriptions in the "Clock and Reset Signals" table.
• Added descriptions in the "Transceiver Mode and Operating Speed Signals" table.
• Changed the "Avalon-MM Interface Signals" table.
• Added signals to the "XGMII Signals" table.
• Added registers to the "PHY Register Definitions" table.
• Added parameters to the "1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core Parameters" table.
Made the following changes to the 1-Gigabit/10-Gigabit Ethernet (GbE) PHY IP Core section:
• Updated the version and release date in the "1G/10GbE Release Information" table.
• Added signals to the "1G/10GbE PHY Top-Level Signals" figure.
• Added signals to the "PHY Interface Signals" figure.
• Added signals to the "Control and Status Signals" table.
• Changed descriptions in the "GMII Interface Ports " table.
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
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Arria
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10 Transceiver PHY User Guide
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