Intel Arria 10 User Manual

Name Direction Clock Domain Description
tx_pma_qpipullup[<
n>-1:0]
Input Asynchronous This port is available if you turn on Enable
tx_pma_qpipullup port (QPI) in the Transceiver Native PHY
IP core Parameter Editor. It is only used for Quick Path
Interconnect (QPI) applications.
tx_pma_qpipulldn[<
n>-1:0]
Input Asynchronous This port is available if you turn on Enable
tx_pma_qpipulldn port (QPI) in the Transceiver Native PHY
IP core Parameter Editor. It is only used for Quick Path
Interconnect (QPI) applications.
tx_pma_txdetectrx[
<n>-1:0]
Input Asynchronous This port is available if you turn on Enable
tx_pma_txdetectrx port (QPI) in the Transceiver Native
PHY IP core Parameter Editor. When asserted, the receiver
detect block in TX PMA detects the presence of a receiver at
the other end of the channel. After receiving the
tx_pma_txdetectrx request, the receiver detect block
initiates the detection process. Use this port for Quick Path
Interconnect (QPI) applications only.
tx_pma_rxfound[<n>
-1:0]
Output Synchronous to
rx_coreclkin or
rx_clkout based
on the
configuration.
This port is available if you turn on Enable
tx_rxfound_pma port (QPI) in the Transceiver Native PHY
IP core Parameter Editor. When asserted, indicates that
the receiver detect block in TX PMA has detected a receiver
at the other end of the channel. Use this port for Quick Path
Interconnect (QPI) applications only.
rx_seriallpbken[<n
>-1:0]
Input Asynchronous This port is available if you turn on Enable rx_seriallpbken
port in the Transceiver Native PHY IP core Parameter
Editor. The assertion of this signal enables the TX to RX
serial loopback path within the transceiver. This signal can be
enabled in Duplex or Simplex mode. If enabled in Simplex
mode, you must drive the signal on both the TX and RX
instances from the same source. Otherwise the design fails
compilation.
Table 46. RX PMA Ports
Name Direction Clock Domain Description
rx_serial_data[<n>
-1:0]
Input N/A Specifies serial data input to the RX PMA.
rx_cdr_refclk0
Input Clock Specifies reference clock input to the RX clock data recovery
(CDR) circuitry.
Optional Ports
rx_cdr_refclk1–
rx_cdr_refclk4
Input Clock Specifies reference clock inputs to the RX clock data recovery
(CDR) circuitry.
rx_analog_reset_ac
k
Output Asynchronous Enables the optional rx_pma_analog_reset_ack output. This
port should not be used for register mode data transfers.
rx_pma_clkout
Output Clock This clock is the recovered parallel clock from the RX CDR
circuitry.
rx_pma_div_clkout
Output Clock The deserializer generates this clock. This is used to drive core
logic, PCS-to-FPGA fabric interface, or both. If you specify a
rx_pma_div_clkout division factor of 1 or 2, this clock output
is derived from the PMA parallel clock (low speed parallel
clock). If you specify a rx_pma_div_clkout division factor of
33, 40, or 66, this clock is derived from the PMA serial clock.
This clock is commonly used when the interface to the RX FIFO
runs at a different rate than the PMA parallel clock (low speed
parallel clock) frequency, such as 66:40 applications.
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
74

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex