Intel Arria 10 User Manual

Table 49. Enhanced TX PCS: Parallel Data, Control, and Clocks
Name Direction Clock Domain Description
tx_parallel_data[
<n>128-1:0]
Input Synchronous to
the clock driving
the write side of
the FIFO
(tx_coreclkin
or tx_clkout)
TX parallel data inputs from the FPGA fabric to the TX PCS. If
you select Enable simplified interface in the Transceiver
Native PHY IP Parameter Editor, tx_parallel_data
includes only the bits required for the configuration you specify.
You must ground the data pins that are not active. For single
width configuration, the following bits are active:
• 32-bit FPGA fabric to PCS interface width:
tx_parallel_data[31:0]. Ground [127:32].
• 40-bit FPGA fabric to PCS interface width:
tx_parallel_data[39:0]. Ground [127:40].
• 64-bit FPGA fabric to PCS interface width:
tx_parallel_data[63:0] Ground [127:64].
For double width configuration, the following bits are active:
• 40-bit FPGA fabric to PCS interface width: data[103:64],
[39:0]. Ground [127:104], [63:40].
• 64-bit FPGA fabric to PCS interface width: data[127:64],
[63:0].
Double-width mode is not supported for 32-bit, 50-bit, and 67-
bit FPGA fabric to PCS interface widths.
unused_tx_paralle
l_data
Input
tx_clkout
Port is enabled, when you enable Enable simplified data
interface. Connect all of these bits to 0. When Enable
simplified data interface is disabled, the unused bits are a
part of tx_parallel_data. Refer to tx_parallel_data to
identify the bits you need to ground.
tx_control[<n><3>
-1:0] or
tx_control[<n><18
>-1:0]
Input Synchronous to
the clock driving
the write side of
the FIFO
(tx_coreclkin
or tx_clkout)
tx_control bits have different functionality depending on the
transceiver configuration rule selected. When Simplified data
interface is enabled, the number of bits in this bus change
because the unused bits are shown as part of the
unused_tx_control port.
Refer to Enhanced PCS TX and RX Control Ports on page 83
section for more details.
unused_tx_contro
l[<n> <15>-1:0]
Input Synchronous to
the clock driving
the write side of
the FIFO
(tx_coreclkin
or tx_clkout)
This port is enabled when you enable Enable simplified data
interface. Connect all of these bits to 0. When Enable
simplified data interface is disabled, the unused bits are a
part of the tx_control.
Refer to tx_control to identify the bits you need to ground.
tx_err_ins
Input
tx_coreclkin
For the Interlaken protocol, you can use this bit to insert the
synchronous header and CRC32 errors if you have turned on
Enable simplified data interface.
When asserted, the synchronous header for that cycle word is
replaced with a corrupted one. A CRC32 error is also inserted if
Enable Interlaken TX CRC-32 generator error insertion is
turned on. The corrupted sync header is 2'b00 for a control
word, and 2'b11 for a data word. For CRC32 error insertion, the
word used for CRC calculation for that cycle is incorrectly
inverted, causing an incorrect CRC32 in the Diagnostic Word of
the Metaframe.
Note that a synchronous header error and a CRC32 error
cannot be created for the Framing Control Words because the
Frame Control Words are created in the frame generator
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
77

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English