Intel Arria 10 User Manual

Name Direction Clock Domain Description
embedded in TX PCS. Both the synchronous header error and
the CRC32 errors are inserted if the CRC-32 error insertion
feature is enabled in the Transceiver Native PHY IP GUI.
tx_coreclkin
Input Clock The FPGA fabric clock. Drives the write side of the TX FIFO. For
the Interlaken protocol, the frequency of this clock could be
from datarate/67 to datarate/32. Using frequency lower than
this range can cause the TX FIFO to underflow and result in
data corruption.
tx_clkout
Output Clock This is a parallel clock generated by the local CGB for non
bonded configurations, and master CGB for bonded
configurations. This clocks the blocks of the TX Enhanced PCS.
The frequency of this clock is equal to the datarate divided by
PCS/PMA interface width.
Table 50. Enhanced RX PCS: Parallel Data, Control, and Clocks
Name Direction Clock Domain Description
rx_parallel_data[<n
>128-1:0]
Output Synchronous
to the clock
driving the
read side of
the FIFO
(rx_coreclk
in or
rx_clkout)
RX parallel data from the RX PCS to the FPGA fabric. If you
select, Enable simplified data interface in the Transceiver
Native PHY IP GUI, rx_parallel_data includes only the bits
required for the configuration you specify. Otherwise, this
interface is 128 bits wide.
When FPGA fabric to PCS interface width is 64 bits, the
following bits are active for interfaces less than 128 bits. You
can leave the unused bits floating or not connected.
• 32-bit FPGA fabric to PCS width: data[31:0].
• 40-bit FPGA fabric to PCS width: data[39:0].
• 64-bit FPGA fabric to PCS width: data[63:0].
When the FPGA fabric to PCS interface width is 128 bits, the
following bits are active:
• 40-bit FPGA fabric to PCS width: data[103:64], [39:0].
• 64-bit FPGA fabric to PCS width: data[127:0].
unused_rx_parallel_
data
Output
rx_clkout
This signal specifies the unused data when you turn on Enable
simplified data interface. When simplified data interface is
not set, the unused bits are a part of rx_parallel_data.
You can leave the unused data outputs floating or not
connected.
rx_control[<n>
<20>-1:0]
Output Synchronous
to the clock
driving the
read side of
the FIFO
(rx_coreclk
in or
rx_clkout)
Indicates whether the rx_parallel_data bus is control or
data.
Refer to the Enhanced PCS TX and RX Control Ports on page
83 section for more details.
unused_rx_control[<
n>10-1:0]
Output Synchronous
to the clock
driving the
read side of
the FIFO
These signals only exist when you turn on Enable simplified
data interface. When simplified data interface is not set, the
unused bits are a part of rx_control. These outputs can be
left floating.
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
78

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English