Intel Arria 10 User Manual

Name Direction Clock Domain Description
(rx_coreclk
in or
rx_clkout)
rx_coreclkin
Input Clock The FPGA fabric clock. Drives the read side of the RX FIFO. For
Interlaken protocol, the frequency of this clock could be from
datarate/67 to datarate/32.
rx_clkout
Output Clock The low speed parallel clock recovered by the transceiver RX
PMA, that clocks the blocks in the RX Enhanced PCS. The
frequency of this clock is equal to data rate divided by
PCS/PMA interface width.
Table 51. Enhanced PCS TX FIFO
Name Direction Clock Domain Description
tx_enh_data_valid[<n>-
1:0]
Input Synchronous to
the clock driving
the write side of
the FIFO
(tx_coreclkin
or tx_clkout)
Assertion of this signal indicates that the TX data is valid.
Connect this signal to 1'b1 for 10GBASE-R without 1588.
For 10GBASE-R with 1588, you must control this signal
based on the gearbox ratio. For Basic and Interlaken, you
need to control this port based on TX FIFO flags so that
the FIFO does not underflow or overflow.
Refer to Enhanced PCS FIFO Operation on page 297 for
more details.
tx_enh_fifo_full[<n>-1
:0]
Output Synchronous to
the clock driving
the write side of
the FIFO
(tx_coreclkin
or tx_clkout)
Assertion of this signal indicates the TX FIFO is full.
Because the depth is always constant, you can ignore this
signal for the phase compensation mode.
Refer to Enhanced PCS FIFO Operation on page 297 for
more details.
tx_enh_fifo_pfull[<n>-
1:0]
Output Synchronous to
the clock driving
the write side of
the FIFO
tx_coreclkin
or tx_clkout
This signal gets asserted when the TX FIFO reaches its
partially full threshold. Because the depth is always
constant, you can ignore this signal for the phase
compensation mode.
Refer to Enhanced PCS FIFO Operation on page 297 for
more details.
tx_enh_fifo_empty[<n>-
1:0]
Output Synchronous to
the clock driving
the write side of
the FIFO
tx_coreclkin
or tx_clkout
When asserted, indicates that the TX FIFO is empty. This
signal gets asserted for 2 to 3 clock cycles. Because the
depth is always constant, you can ignore this signal for
the phase compensation mode.
Refer to Enhanced PCS FIFO Operation on page 297 for
more details.
tx_enh_fifo_pempty[<n>
-1:0]
Output Synchronous to
the clock driving
the write side of
the FIFO
tx_coreclkin
or tx_clkout
When asserted, indicates that the TX FIFO has reached its
specified partially empty threshold. When you turn this
option on, the Enhanced PCS enables the
tx_enh_fifo_pempty port, which is asynchronous. This
signal gets asserted for 2 to 3 clock cycles. Because the
depth is always constant, you can ignore this signal for
the phase compensation mode.
Refer to Enhanced PCS FIFO Operation on page 297 for
more details.
Table 52. Enhanced PCS RX FIFO
Name Direction Clock Domain Description
rx_enh_data_valid[<n>
-1:0]
Output Synchronous to
the clock driving
the read side of
When asserted, indicates that rx_parallel_data is
valid. Discard invalid RX parallel data
whenrx_enh_data_valid signal is low.
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
79

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English