Table 216. Generate Options Parameters
Parameter Range
Generate parameter documentation file On / Off
Related Information
Using the Arria 10 Transceiver Native PHY IP Core on page 45
2.9.1.3. How to Enable Low Latency in Basic Enhanced PCS
In the Parameter Editor, use the following settings to enable low latency:
1. Select the Enable 'Enhanced PCS' low latency mode option.
2. Select one of the following gear ratios:
Single-width mode: 32:32, 40:40, 64:64, 66:40, 66:64, or 64:32
Double-width mode: 40:40, 64:64, or 66:64
3. Select Phase_compensation in the TX and RX FIFO mode list.
4. If you need the Scrambler and Descrambler features, enable Block Synchronize
and use the 66:32, 66:40, or 66:64 gear ratio.
2.9.1.4. Enhanced PCS FIFO Operation
Phase Compensation Mode
Phase compensation mode ensures correct data transfer between the core clock and
parallel clock domains. The read and write sides of the TX Core or RX Core FIFO must
be driven by the same clock frequency. The depth of the TX or RX FIFO is constant in
this mode. Therefore, the TX Core or RX Core FIFO flag status can be ignored. You can
tie tx_fifo_wr_en or rx_data_valid to 1.
Basic Mode
Basic mode allows you to drive the write and read side of a FIFO with different clock
frequencies. tx_coreclkin or rx_coreclkin must have a minimum frequency of
the lane data rate divided by 66. The frequency range for tx_coreclkin or
rx_coreclkin is (data rate/32) to (data rate/66). For best results, Intel
recommends that tx_coreclkin or rx_coreclkin be set to (data rate/32). Monitor
the FIFO flag to control write and read operations.
For TX FIFO, assert tx_enh_data_valid with the tx_fifo_pfull signal going low.
This can be done with the following example assignment:
assign tx_enh_data_valid = ~tx_fifo_pfull;
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
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10 Transceiver PHY User Guide
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