Intel Arria 10 User Manual

Parameter Range
Enable rx_enh_fifo_del port (10GBASE-R) On / Off
Enable rx_enh_fifo_insert port (10GBASE-R) On / Off
Enable rx_enh_fifo_rd_en port (Interlaken) On / Off
Enable rx_enh_fifo_align_val port (Interlaken) On / Off
Enable rx_enh_fifo_align_cir port (Interlaken) On / Off
Enable TX 64b/66b encoder On / Off
Enable RX 64b/66b decoder On / Off
Enable TX sync header error insertion On / Off
Enable RX block synchronizer On / Off
Enable rx_enh_blk_lock port On / Off
Enable TX data bitslip On / Off
Enable TX data polarity inversion On / Off
Enable RX data bitslip On / Off
Enable RX data polarity inversion On / Off
Enable tx_enh_bitslip port On / Off
Enable rx_bitslip port On / Off
Enable RX KR-FEC error marking On / Off
Error marking type 10G, 40G
Enable KR-FEC TX error insertion On / Off
KR-FEC TX error insertion spacing On / Off
Enable tx_enh_frame port On / Off
Enable rx_enh_frame port On / Off
Enable rx_enh_frame_dian_status port On / Off
Table 215. Dynamic Reconfiguration Parameters
Parameter Range
Enable dynamic reconfiguration On / Off
Share reconfiguration interface On / Off
Enable Altera Debug Master Endpoint On / Off
Enable embedded debug On / Off
Enable capability registers On / Off
Set user-defined IP identifier number
Enable control and status registers On / Off
Enable prbs soft accumulators On / Off
Configuration file prefix text string
Generate SystemVerilog package file On / Off
Generate C header file On / Off
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
296

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex