Intel Arria 10 User Manual

Parameter Range
Enable rx_pma_div_clkout port On / Off
rx_pma_div_clkout division factor Disabled, 1, 2, 33, 40, 66
Enable rx_pma_clkslip port On / Off
Enable rx_pma_qpipulldn port (QPI) On / Off
Enable rx_is_lockedtodata port On / Off
Enable rx_is_lockedtoref port On / Off
Enable rx_set_locktodata and rx_set_locktoref ports On / Off
Enable rx_serialpbken port On / Off
Enable PRBS verifier control and status ports On / Off
Table 214. Enhanced PCS Parameters
Parameter Range
Enhanced PCS/PMA interface width 32, 40, 64
Note: Basic with KR FEC allows 64 only
FPGA fabric/Enhanced PCS interface width 32, 40, 50, 64, 66, 67
Note: Basic with KR FEC allows 66 only
Enable Enhanced PCS low latency mode On / Off
Enable RX/TX FIFO double width mode On / Off
TX FIFO mode Phase compensation, Register, Interlaken, Basic, Fast
register
Note: Only Basic Enhanced and Basic Enhanced with
KRFEC are valid.
TX FIFO partially full threshold 10, 11, 12, 13, 14, 15
TX FIFO partially empty threshold 1, 2, 3, 4, 5
Enable tx_enh_fifo_full port On / Off
Enable tx_enh_fifo_pfull port On / Off
Enable tx_enh_fifo_empty port On / Off
Enable tx_enh_fifo_pempty port On / Off
RX FIFO mode Phase Compensation, Register, Basic
RX FIFO partially full threshold 0 to 31
RX FIFO partially empty threshold 0 to 31
Enable RX FIFO alignment word deletion (Interlaken) On / Off
Enable RX FIFO control word deletion (Interlaken) On / Off
Enable rx_enh_data_valid port On / Off
Enable rx_enh_fifo_full port On / Off
Enable rx_enh_fifo_pfull port On / Off
Enable rx_enh_fifo_empty port On / Off
Enable rx_enh_fifo_pempty port On / Off
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
295

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex