Intel Arria 10 User Manual

Name Direction Clock Domain Description
the FIFO
rx_coreclkin
or rx_clkout
This option is available when you select the following
parameters:
• Enhanced PCS Transceiver configuration rules
specifies Interlaken
• Enhanced PCS Transceiver configuration rules
specifies Basic, and RX FIFO mode is Phase
compensation
• Enhanced PCS Transceiver configuration rules
specifies Basic, and RX FIFO mode is Register
Refer to Enhanced PCS FIFO Operation on page 297
for more details.
rx_enh_fifo_full[<n>-
1:0]
Output Synchronous to
the clock driving
the read side of
the FIFO
rx_coreclkin
or rx_clkout
When asserted, indicates that the RX FIFO is full. This
signal gets asserted for 2 to 3 clock cycles.Because
the depth is always constant, you can ignore this
signal for the phase compensation mode.
Refer to Enhanced PCS FIFO Operation on page 297
for more details.
rx_enh_fifo_pfull[<n>
-1:0]
Output Synchronous to
the clock driving
the read side of
the FIFO
rx_coreclkin
or rx_clkout
When asserted, indicates that the RX FIFO has
reached its specified partially full threshold. This signal
gets asserted for 2 to 3 clock cycles. Because the
depth is always constant, you can ignore this signal
for the phase compensation mode.
Refer to Enhanced PCS FIFO Operation on page 297
for more details.
rx_enh_fifo_empty[<n>
-1:0]
Output Synchronous to
the clock driving
the read side of
the FIFO
rx_coreclkin
or rx_clkout
When asserted, indicates that the RX FIFO is empty.
Because the depth is always constant, you can ignore
this signal for the phase compensation mode.
Refer to Enhanced PCS FIFO Operation on page 297
for more details.
rx_enh_fifo_pempty[<n
>-1:0]
Output Synchronous to
the clock driving
the read side of
the FIFO
rx_coreclkin
or rx_clkout
When asserted, indicates that the RX FIFO has
reached its specified partially empty threshold.
Because the depth is always constant, you can ignore
this signal for the phase compensation mode.
Refer to Enhanced PCS FIFO Operation on page 297
for more details.
rx_enh_fifo_del[<n>-1
:0]
Output Synchronous to
the clock driving
the read side of
the FIFO
rx_coreclkin
or rx_clkout
When asserted, indicates that a word has been deleted
from the RX FIFO. This signal gets asserted for 2 to 3
clock cycles. This signal is used for the 10GBASE-R
protocol.
rx_enh_fifo_insert[<n
>-1:0]
Output Synchronous to
the clock driving
the read side of
the FIFO
rx_coreclkin
or rx_clkout
When asserted, indicates that a word has been
inserted into the RX FIFO. This signal is used for the
10GBASE-R protocol.
rx_enh_fifo_rd_en[<n>
-1:0]
Output Synchronous to
the clock driving
the read side of
the FIFO
rx_coreclkin
or rx_clkout
For Interlaken only, when this signal is asserted, a
word is read form the RX FIFO. You need to control
this signal based on RX FIFO flags so that the FIFO
does not underflow or overflow.
rx_enh_fifo_align_va
l[<n>-1:0]
Input Synchronous to
the clock driving
the read side of
When asserted, indicates that the word alignment
pattern has been found. This signal is only valid for
the Interlaken protocol.
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
80

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English