Intel Arria 10 User Manual

Name Direction Clock Domain Description
the FIFO
rx_coreclkin
or rx_clkout
rx_enh_fifo_align_cl
r[<n>-1:0]
Input Synchronous to
the clock driving
the read side of
the FIFO
rx_coreclkin
or rx_clkout
When asserted, the FIFO resets and begins searching
for a new alignment pattern. This signal is only valid
for the Interlaken protocol. Assert this signal for at
least 4 cycles.
Table 53. Interlaken Frame Generator, Synchronizer, and CRC32
Name Direction Clock Domain Description
tx_enh_frame[<n>-1:0]
Output
tx_clkout
Asserted for 2 or 3 parallel clock cycles to indicate the
beginning of a new metaframe.
tx_enh_frame_diag_stat
us[<n> 2-1:0]
Input
tx_clkout
Drives the lane status message contained in the framing
layer diagnostic word (bits[33:32]). This message is
inserted into the next diagnostic word generated by the
frame generator block. This bus must be held constant for 5
clock cycles before and after the tx_enh_frame pulse. The
following encodings are defined:
• Bit[1]: When 1, indicates the lane is operational. When
0, indicates the lane is not operational.
• Bit[0]: When 1, indicates the link is operational. When
0, indicates the link is not operational.
tx_enh_frame_burst_en[
<n>-1:0]
Input
tx_clkout
If Enable frame burst is enabled, this port controls frame
generator data reads from the TX FIFO to the frame
generator. It is latched once at the beginning of each
Metaframe. If the value of tx_enh_frame_burst_en is 0,
the frame generator does not read data from the TX FIFO
for current Metaframe. Instead, the frame generator inserts
SKIP words as the payload of Metaframe. When
tx_enh_frame_burst_en is 1, the frame generator reads
data from the TX FIFO for the current Metaframe. This port
must be held constant for 5 clock cycles before and after
the tx_enh_frame pulse.
rx_enh_frame[<n>-1:0]
Output
rx_clkout
When asserted, indicates the beginning of a new received
Metaframe. This signal is pulse stretched.
rx_enh_frame_lock[<n>-
1:0]
Output
rx_clkout
When asserted, indicates the Frame Synchronizer state
machine has achieved Metaframe delineation. This signal is
pulse stretched.
rx_enh_frame_diag_stat
us[2 <n>-1:0]
Output
rx_clkout
Drives the lane status message contained in the framing
layer diagnostic word (bits[33:32]). This signal is latched
when a valid diagnostic word is received in the end of the
Metaframe while the frame is locked. The following
encodings are defined:
• Bit[1]: When 1, indicates the lane is operational. When
0, indicates the lane is not operational.
• Bit[0]: When 1, indicates the link is operational. When
0, indicates the link is not operational.
rx_enh_crc32_err[<n>-1
:0]
Output
rx_clkout
When asserted, indicates a CRC error in the current
Metaframe. Asserted at the end of current Metaframe. This
signal gets asserted for 2 or 3 cycles.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
81

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex