Intel Arria 10 User Manual

Table 54. 10GBASE-R BER Checker
Name Direction Clock Domain Description
rx_enh_highber[<n>-1:0
]
Output
rx_clkout
When asserted, indicates a bit error rate that is greater
than 10
-4
. For the 10GBASE-R protocol, this BER rate
occurs when there are at least 16 errors within 125 µs.
This signal gets asserted for 2 to 3 clock cycles.
rx_enh_highber_clr_cn
t[<n>-1:0]
Input
rx_clkout
When asserted, clears the internal counter that indicates
the number of times the BER state machine has entered
the BER_BAD_SH state.
rx_enh_clr_errblk_coun
t[<n>-1:0] (10GBASE-R
and FEC)
Input
rx_clkout
When asserted the error block counter resets to 0.
Assertion of this signal clears the internal counter that
counts the number of times the RX state machine has
entered the RX_E state. In modes where the FEC block is
enabled, the assertion of this signal resets the status
counters within the RX FEC block.
Table 55. Block Synchronizer
Name Direction Clock Domain Description
rx_enh_blk_lock<n>-1:0
]
Output
rx_clkout
When asserted, indicates that block synchronizer has
achieved block delineation. This signal is used for
10GBASE-R and Interlaken.
Table 56. Gearbox
Name Direction Clock Domain Description
rx_bitslip[<n>-1:0]
Input
rx_clkout The rx_parallel_data slips 1 bit for every positive edge
of the rx_bitslip input. Keep the minimum interval
between rx_bitslip pulses to at least 20 cycles. The
maximum shift is < pcswidth -1> bits, so that if the PCS is
64 bits wide, you can shift 0-63 bits.
tx_enh_bitslip[<n>-1:0
]
Input
rx_clkout
The value of this signal controls the number of bits to slip
the tx_parallel_data before passing to the PMA.
Table 57. KR-FEC
Name Direction Clock Domain Description
tx_enh_frame[<n>-1:0]
Output
tx_clkout
Asynchronous status flag output of TX KR-FEC that signifies
the beginning of generated KR FEC frame
rx_enh_frame[<n>-1:0]
Output
rx_clkout
Asynchronous status flag output of RX KR-FEC that
signifies the beginning of received KR FEC frame
rx_enh_frame_diag_stat
us
Output
rx_clkout
Asynchronous status flag output of RX KR-FEC that
indicates the status of the current received frame.
• 00: No error
• 01: Correctable Error
• 10: Un-correctale error
• 11: Reset condition/pre-lock condition
Related Information
• ATX PLL IP Core on page 354
• CMU PLL IP Core on page 370
• fPLL IP Core on page 362
• Ports and Parameters on page 535
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
82

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex