Intel Arria 10 User Manual

Document
Version
Changes
• Changed the "Recalibration Sequence when the Transceiver Reference Clock or Data Rate Changes"
figure.
• Added steps to the "User Recalibration" section.
• Updated the "Transceiver Channel PMA Calibration Registers for Production Devices" table.
• Updated the "Fractional PLL Calibration Registers" table.
• Updated the "ATX PLL Calibration Registers" table.
• Changed the description in the "ATX PLL Calibration Registers" section.
• Added description to the "Capability Registers" section.
• Changed the "Power-up Calibration Sequence for Non-PCIe Hard IP (HIP) Channels" figure.
• Changed the "Power-up Calibration Sequence for PCIe HIP and non-PCIe Channels" figure.
• Removed some steps from the "User Recalibration" section.
• Removed some steps from the "ATX PLL Recalibration" section.
• Removed some steps from the "Fractional PLL Recalibration" section.
• Removed some steps from the "PMA Recalibration" section.
• Removed the "Check Calibration Status" section.
2015.05.11 Made the following changes:
• Changed register offsets globally.
• Changed the description in the "Reconfiguration Interface and Arbitration with PreSICE Calibration
Engine" section.
• Changed the description in the "Calibration Registers" section.
• Changed the descriptions and added a bit in the "Avalon-MM Interface Arbitration Registers" table.
• Changed the descriptions in the "Transceiver Channel Calibration Registers" table.
• Changed the descriptions in the "Fractional PLL Calibration Registers" table.
• Changed the descriptions in the "ATX PLL Calibration Registers" table.
• Added the "Power-up Calibration Sequence for Non-PCIe Hard IP (HIP) Channels" and "Power-up
Calibration Sequence for PCIe HIP and non-PCIe Channels" figures.
• Changed "Avalon-MM interface" to "internal configuration bus" in the "User Recalibration" section.
• Changed "Avalon-MM interface" to "internal configuration bus" in the "ATX PLL Recalibration"
section.
• Changed the bit to calibrate the fPLL and changed "Avalon-MM interface" to "internal configuration
bus" in the "Fractional PLL Recalibration" section.
• Changed "Avalon-MM interface" to "internal configuration bus" in the "CMU or CDR PLL
Recalibration" section.
• Changed the addresses in the "User Recalibration" section.
• Changed the addresses in the "ATX PLL Recalibration" section.
• Changed the addresses in the "Fractional PLL Recalibration" section.
• Changed the addresses in the "CDR/CMU PLL Recalibration" section.
• Changed the addresses and added descriptions in the "PMA Recalibration" section.
• Changed the addresses in the "Check Calibration Status" section.
• Changed "Avalon-MM interface" to "internal configuration bus" in the "PMA Recalibration" section.
• Added the "Capability Registers" section.
2014.12.15 Initial release.
7. Calibration
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
584

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex