Table 286. Control Registers for the Native PHY IP Core
Address Type Register Description
0x2E0[0] RW
set_rx_locktodata Asserts the set_rx_locktodata signal to the
receiver. 1'b1 sets the ADME set_rx_locktodata
register. See override_set_rx_locktodata.
0x2E0[1] RW
set_rx_locktoref Asserts the set_rx_locktoref signal to the
receiver. 1'b1 sets the ADME set_rx_locktoref
register. See override_set_rx_locktoref row
below.
0x2E0[2] RW
override_set_rx_loc
ktodata
Selects whether the receiver listens to the ADME
set_rx_locktodata register or the
rx_set_locktodata port. 1'b1 indicates that the
receiver listens to the ADME set_rx_locktodata
register.
0x2E0[3] RW
override_set_rx_loc
ktoref
Selects whether the receiver is listens to the AMDE
set_rx_locktoref register or the
rx_set_locktoref port. 1'b1 indicates that the
receiver listens to the ADME set_rx_locktoref
register.
0x2E1[0] RW
rx_seriallpbken Enables the rx_seriallopbken feature in the
transceiver. 1’b1 enables reverse serial loopback.
0x2E2[0] RW
rx_analogreset Drives rx_analogreset when the override is set.
0x2E2[1] RW
rx_digitalreset Drives rx_digitalreset when the override is set.
0x2E2[2] RW
tx_analogreset Drives tx_analogreset when the override is set.
0x2E2[3] RW
tx_digitalreset Drives tx_digitalreset when the override is set.
0x2E2[4] RW
override_rx_analogr
eset
Selects whether the receiver listens to the ADME
rx_analogreset register or the rx_analogreset
port. 1'b1 indicates the receiver listens to the ADME
rx_analogreset register.
0x2E2[5] RW
override_rx_digital
reset
Selects whether the receiver listens to the ADME
rx_digitalreset register or the
rx_digitalreset port. 1'b1 indicates the receiver
listens to the ADME rx_digitalreset register.
0x2E2[6] RW
override_tx_analogr
eset
Selects whether the receiver listens to the ADME
tx_analogreset register or the tx_analogreset
port. 1'b1 indicates the receiver listens to the ADME
tx_analogreset register.
0x2E2[7] RW
override_tx_digital
reset
Selects whether the receiver listens to the ADME
tx_digitalreset register or the
tx_digitalreset port. 1'b1 indicates the receiver
listens to the ADME tx_digitalreset register.
Table 287. Status Registers for the Native PHY IP Core
Address Type Register Description
0x280[0] RO
rx_is_lockedtodata
Shows the status of the current channel’s
rx_is_lockedtodata signal. 1’b1 indicates the
receiver is locked to the incoming data.
0x280[1] RO
rx_is_lockedtoref
Shows the status of the current channel’s
rx_is_lockedtoref signal. 1’b1 indicates the
receiver is locked to the reference clock.
continued...
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
546
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