Address Type Register Description
0x281[0] RO
tx_cal_busy
Shows the status of the transmitter calibration
status. 1’b1 indicates the transmitter calibration is in
progress.
0x281[1] RO
rx_cal_busy
Shows the status of the receiver calibration status.
1’b1 indicates the receiver calibration is in progress.
0x281[2] RO
avmm_busy
Shows the status of the internal configuration bus
arbitration. 1’b1 indicates PreSICE has control of the
internal configuration bus. 1'b0 indicates the user
has control of the internal configuration bus. Refer to
the Arbitration section for more details. For more
details about calibration registers and performing
user recalibration, refer to the Calibration chapter.
The following control and status registers are available for the PLL IP cores.
Table 288. Control Registers for the PLL IP Cores
Address Type Register Description
0x2E0[0] RW
pll_powerdown
Drives the PLL powerdown when the Override is set.
0x2E0[1] RW
override_pll_powerd
own
Selects whether the receiver listens to the ADME
pll_powerdown register or the pll_powerdown
port. 1’b1 indicates the receiver listens to the ADME
pll_powerdown.
Table 289. Status Registers for the PLL IP Cores
Address Type Register Description
0x280[0] RO
pll_locked
Indicates if the PLL is locked. 1'b1 indicates the PLL
is locked.
0x280[1] RO
pll_cal_busy
Indicates the calibration status. 1'b1 indicates the
PLL is currently being calibrated.
0x280[2] RO
avmm_busy
Shows the status of the internal configuration bus
arbitration. 1’b1 indicates PreSICE has control of the
internal configuration bus. 1'b0 indicates the user
has control of the internal configuration bus. Refer to
the Arbitration section for more details.
Related Information
Arbitration on page 512
6.15.2.3. PRBS Soft Accumulators
The Pseudo Random Binary Sequence (PRBS) soft accumulators are used in
conjunction with the hard PRBS blocks in the transceiver channel. This section
describes the soft logic that can be added to the Native PHY IP core. To enable this
option, turn on the Enable PRBS Soft Accumulators option in the Native PHY IP
Parameter Editor.
The PRBS soft accumulator has three control bits (Enable, Reset, and Snapshot) and
one status bit (PRBS Done).
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
Intel
®
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®
10 Transceiver PHY User Guide
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