Intel Arria 10 User Manual

• Enable bit—used to turn on the accumulation logic. This bit is also used for
selective error accumulation and to pause the sequence.
• Reset bit—resets the PRBS polynomial and the bit and error accumulators. It also
resets the snapshot registers if independent channel snapshots are used.
• Snapshot bit—captures the current value of the accumulated bits and the errors
simultaneously. This neutralizes the impact of the added read time when the
Avalon-MM interface is used. Capturing a snapshot provides an accurate error
count with respect to the bit count at a specific time.
• PRBS Done bit—indicates the PRBS checker has had sufficient time to lock to the
incoming pattern.
For example, to capture the accumulated errors at any instance of time and read them
back, you can perform the following operations.
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Perform read-modify-write to address 0x300 and set bit 0 to 1'b1. This action
enables the error and bit counters.
3. To capture the errors accumulated at a particular instant, perform read-modify-
write to address 0x300 and set bit 2 to 1'b1. This takes a snapshot of the error
counters and stores the value to the error count registers.
4. To read the number of errors accumulated when the snapshot was captured,
perform a read from the corresponding error registers 0x301 to 0x307.
5. To reset the bit and error accumulators, perform a read-modify-write to address
0x300 bit 1.
6. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Note: You can enable the error and bit counters (0x300[0]) and capture the accumulated
bits and errors at different times. The error count registers and bit count registers are
updated with the latest counter values as long as the counter enable bit is set.
Use the PRBS soft accumulators to count the number of accumulated bits and errors
when the hard PRBS blocks are used. PRBS soft accumulators are word-based counter.
The value read out from the PRBS soft accumulators represent the number of words
counted. Hence, in order to obtain the total accumulated bit, user needs to multiply
the value read out from the Accumulated bit pass through count [49:0] registers with
the width of PCS-PMA interface. For Accumulated error count [49:0] registers, it
counts one as long as there are bit errors in a word (be it one bit error in a word or all
the bits in a word are erroneous). Hence, the Accumulated error count [49:0]
registers do not give absolute bit errors counted. For each count, the absolute bit
errors could range from one to the width of PCS-PMA interface.
For more information about using the hard PRBS blocks, refer to the "Using Data
Pattern Generators and Checkers" section.
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex