Intel Arria 10 User Manual

Rules for Merging Reconfiguration Interfaces Across Multiple IP Cores
To merge reconfiguration interfaces across multiple IP blocks, you must follow these
rules:
1. The control signals for the reconfiguration interfaces of the IP blocks must be
driven by the same source. The reconfig_clk, reconfig_reset,
reconfig_write, reconfig_read, reconfig_address, and
reconfig_writedata ports of the two interfaces to be merged must be driven
from the same source.
2. You must make a QSF assignment to manually specify which two reconfiguration
interfaces are to be merged.
a. Use the XCVR_RECONFIG_GROUP assignment.
b. Set the To field of the assignment to either the reconfiguration interfaces of
the instances to be merged or to the pin names. The reconfiguration interface
has the string twentynm_hssi_avmm_if_inst.
c. Assign the two instances to be merged to the same reconfiguration group.
You cannot merge multiple reconfiguration interfaces when ADME, optional
reconfiguration logic, or embedded reconfiguration streamer are enabled in the Native
PHY IP core.
(62)
You cannot merge the TX and RX channels when the Shared reconfiguration
interface parameter is enabled in the Native PHY IP core Parameter Editor. You can
merge channels only if the reconfiguration interfaces are independent.
Refer to the following two examples to merge reconfiguration interfaces.
Example 3. Using reconfiguration interface names
This example shows how to merge a transmit-only Native PHY instance with a receive-
only instance using the reconfiguration interface names. These instances are assigned
to reconfiguration group 0.
For Native PHY 0—transmit-only instance:
set_instance_assignment -name XCVR_RECONFIG_GROUP 0 -to
topdesign:topdesign_inst|<TX only instance name>*twentynm_hssi_avmm_if_inst*
For Native PHY 1—receive-only instance to be merged with Native PHY 0:
set_instance_assignment -name XCVR_RECONFIG_GROUP 0 -to
topdesign:topdesign_inst|<RX only instance name>*twentynm_hssi_avmm_if_inst*
Example 4. Using pin names
This example shows how to merge a transmit-only Native PHY instance with a receive-
only instance using pin names. These instances are assigned to reconfiguration group
1.
For Native PHY 0—transmit-only instance:
set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to tx[0]
(62)
Please refer to Calibration section on how to calibrate when those features are not available.
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex