Intel Arria 10 User Manual

To enable the Quartus Prime software to close timing more accurately in this example,
the following constraints must be created:
•
create_clock -name tx_clkout_enh -period 5.12 [get_pins
{native_inst|xcvr_native_a10_0|
g_xcvr_native_insts[0].twentynm_xcvr_native_inst|
twentynm_xcvr_native_inst|inst_twentynm_pcs|
gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_p
ld_pcs_interface|pld_pcs_tx_clk_out}] -add
This constraint creates the tx_clkout clock that is used to clock the core logic B
in the FPGA fabric.
•
create_clock -name rx_clkout_enh –period 5.12 [get_pins
{native_inst|xcvr_native_a10_0|
g_xcvr_native_insts[0].twentynm_xcvr_native_inst|
twentynm_xcvr_native_inst|inst_twentynm_pcs|
gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_p
ld_pcs_interface|pld_pcs_rx_clk_out}] -add
This constraint creates the rx_clkout clock that is used to clock the core logic B
in the FPGA fabric.
•
set_false_path -from [get_clocks {tx_clkout_enh}] -to
[get_registers <Core Logic A>]
Based on how the clocks are connected in the design, you might have to include
additional constraints to set false paths from the registers in the core logic to the
clocks.
•
set_false_path -from [get_clocks {rx_clkout_enh}] -to
[get_registers <Core Logic A>]
Based on how the clocks are connected in the design, you may have to include
additional constraints to set false paths from the registers in the core logic to the
clocks.
•
set_false_path -from [get_clocks {tx_clkout}] -to
[get_registers <Core Logic B>]
Based on how the clocks are connected in the design, you may have to include
additional constraints to set false paths from the registers in the core logic to the
clocks.
•
set_false_path -from [get_clocks {rx_clkout}] -to
[get_registers <Core Logic B>]
Based on how the clocks are connected in the design, you may have to include
additional constraints to set false paths from the registers in the core logic to the
clocks.
Note: If any of the profile or configuration switch involves switching from FIFO to
the register mode, then the false paths should be set between the PCS-PMA
interface register and the core logic because the common clock point is
within the PCS-PMA interface.
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
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®
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex