Figure 23. Native PHY IP Core Parameter Editor
Documentation
Presets
General
Options
Common
PMA Options
Datapath
Options
PMA/PCS, Dynamic Reconfiguration, Optional Analog PMA Settings, and General Options
Note: Although the Quartus Prime software provides legality checks, the supported FPGA
fabric to PCS interface widths and the supported data rates are pending
characterization.
Related Information
• Configure the PHY IP Core on page 35
• Interlaken on page 94
• Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 on page 112
• 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants on
page 124
• 10GBASE-KR PHY IP Core on page 135
• 1-Gigabit/10-Gigabit Ethernet (GbE) PHY IP Core on page 164
• PCI Express (PIPE) on page 229
• CPRI on page 279
• Using the "Basic (Enhanced PCS)" and "Basic with KR FEC" Configurations of
Enhanced PCS on page 289
• Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard
PCS on page 300
• Design Considerations for Implementing Arria 10 GT Channels on page 319
• PMA Parameters on page 51
• Presets on page 48
• General and Datapath Parameters on page 48
• Enhanced PCS Ports on page 76
• Standard PCS Ports on page 86
• PMA Ports on page 73
• How to Place Channels for Pipe Configuration on page 268
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
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