Intel Arria 10 User Manual

preset that matches your protocol configuration as a starting point. Presets are PHY IP
configuration settings for various protocols that are stored in the IP Parameter
Editor. Presets are explained in detail in the Presets section below.
You can also configure the PHY IP by selecting an appropriate Transceiver
Configuration Rule. The transceiver configuration rules check the valid combinations
of the PCS and PMA blocks in the transceiver PHY layer, and report errors or warnings
for any invalid settings.
Use the Native PHY IP core to instantiate the following PCS options:
• Standard PCS
• Enhanced PCS
• PCIe Gen3 PCS
• PCS Direct
Based on the Transceiver Configuration Rule that you select, the PHY IP core selects
the appropriate PCS. The PHY IP core allows you to select all the PCS blocks if you
intend to dynamically reconfigure from one PCS to another. Refer to General and
Datapath Parameters section for more details on how to enable PCS blocks for
dynamic reconfiguration. Refer to the How to Place Channels for PIPE Configuration
section or the PCIE solutions guides on restrictions on placement of transceiver
channels next to active banks with PCI Express interfaces that are Gen3 capable..
After you configure the PHY IP core in the Parameter Editor, click Generate HDL to
generate the IP instance. The top level file generated with the IP instance includes all
the available ports for your configuration. Use these ports to connect the PHY IP core
to the PLL IP core, the reset controller IP core, and to other IP cores in your design.
Figure 22. Native PHY IP Core Ports and Functional Blocks
Reconfiguration
Registers
Enhanced PCS
Transmit and Receive Clocks
Standard PCS
PCIe Gen3
PCS
Transmit
PMA
Receive
PMA
Reset Signals
Transmit Parallel Data
Reconfiguration Interface
Transmit Serial Data
Receive Serial Data
Receive Parallel Data
PCS-Direct
Nios II
Calibration
Calibration Signals
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
46

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex